From patchwork Thu Jan 28 08:23:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 372544 Delivered-To: patch@linaro.org Received: by 2002:a17:906:24d5:0:0:0:0 with SMTP id f21csp653488ejb; Thu, 28 Jan 2021 00:38:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJxiK/aqvKwM/C/+SBl9KX+qNGVISlBcG1BCKGFNbLhR2p4HAqcIATAW6VmKhxF5ncCDNF/D X-Received: by 2002:a25:8307:: with SMTP id s7mr24946162ybk.219.1611823095749; Thu, 28 Jan 2021 00:38:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611823095; cv=none; d=google.com; s=arc-20160816; b=twMCt8AJhroJUIowal2jurfVEirCCAfoT4SBw7tB8TzJ3jfjxY30WPRdH+URGjFSOG QOsPLZ3PpNTC0YEZXejJCBcD2UDGtg4AEZ3PlsGzWCtCXs8Ety6zjIO12XJRKVKb+CwY +T6+knVrq54gB8lz7rW+Y/GmL+UmHsU+PXr2g+j12qu65xGak2yCYAwENI2N/wQoV96Q 2JbAf2V2eGBlgo7H5ngIH1yRu3eY+UD/Ac5OM2az/O+lvbGt2lro/JZhAgl7/7mrsBK6 a4Mv0RyhJchip6rwz1h8HZFBeX2SOIpCDMNrkLCl54qBWKBiEEwc9iZYaG9m4jc0NEo3 CF9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=m2ze6FL+5Rg8ehBHjUThMYSDxbo0AgwLwhZ3Mex+2Fk=; b=LFMWTQVfY/qu9pcRu6wRRFpmHpjEmwQ08phc6Q7GacA21otfmTnFVdBgW1Aedk4XCP jC1mFIt+1S4yrb3mW+9gq/KJKqsuzpOXyq4zGEXLJ9gojqm0+jH3j5qgk6BmpnEyoVr0 chnYBxHAWLdWcy/xNEkWS3M7jilh9aZjWby9gUDSEzGXCTrUKvGXWjQSsnVWHtQTxT1l OQuNrMRU/1ajsWZcnFN5MgdL+5Am57zfLY+y8vrOuQM7p4ZhzDeldlrCEiYdeJfXdjYw gzVk7LGJVPW3H6UOhEPHthoNUXZG/V4aZZxeadAdCy+cOdVO928qdwoG4buFVT/kWh3N DNJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hRJWj2Tu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w1si5023623ybp.206.2021.01.28.00.38.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jan 2021 00:38:15 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hRJWj2Tu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l52oh-0004NV-5I for patch@linaro.org; Thu, 28 Jan 2021 03:38:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l52b7-0006MX-Ii for qemu-devel@nongnu.org; Thu, 28 Jan 2021 03:24:13 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:41893) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l52b4-0005nk-28 for qemu-devel@nongnu.org; Thu, 28 Jan 2021 03:24:13 -0500 Received: by mail-pf1-x436.google.com with SMTP id q20so3523033pfu.8 for ; Thu, 28 Jan 2021 00:24:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m2ze6FL+5Rg8ehBHjUThMYSDxbo0AgwLwhZ3Mex+2Fk=; b=hRJWj2TuVDLgyxPGDzfoWgPf/W/mp8+JQiAjBS9J2XqZz7EUZua2GNUrjlixVz58p2 8orQuMRaBkTX7gUm4SMSLUyrxsMYpFlTMGAdlWF7IJL/63Y8z3DCuuGwF9j5t8htlnIY 08lDpsFVxvFvFpgdmU7JHJzLm0oolTyCQCsTDnR2O9PgBKoDjbiMkQWCrvGG16GaPuME vPsH1PvHtemV/64t885KLH9Gok8WxUi/J0xmf8AubC1C7TWonyFDpXOUb4jdNI45cpmD jHtX7GEeEsX5lqXYBN5O9X+8f91JNgXmhuaGDUDf4+dc4N8xvhkLtGcnI0kzeRC1HfOS QTXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m2ze6FL+5Rg8ehBHjUThMYSDxbo0AgwLwhZ3Mex+2Fk=; b=uXpGCHi55ZR7LShrdw1cQaiDw8H9xt9gdtbSTcUt7WFK+4fkb+NtkSEzktDhLEa+/f Ed9rYhDLgappdxC6PEVTWH7gLQVNEF4Yut8qcFRboRRFndg3kQNu85EpGX0moyKhHwBb I4+sy8IMWa6L5a/ZHZSIGmU7UMPq2R1jfw9ZpoASSjFXVUVsm6kBGovVlQUH/QcQ93Bi ZpEz1crYfZvjsxKp/mRekt+wMwEnF2g2DkWwXWdB2OHA4jbyjhWQOQNUnLkfQ+DEx0NQ wFgnHIX6vUtlWqGiOgHPvVBxJG1L1Spnbnsjb26xI5HyCjcL1TSBJr+sI4BvpfwR/I3q yIHA== X-Gm-Message-State: AOAM5312CTbpYW/HiLdj0nUYM9FPh2l4jtfhK9vYUBERJN174plHr5CM 3fgdCpahPjKXJ4vexh1nOCzaWXiruqNRojJB X-Received: by 2002:a62:5a86:0:b029:1ae:6b45:b6a9 with SMTP id o128-20020a625a860000b02901ae6b45b6a9mr14555952pfb.7.1611822248455; Thu, 28 Jan 2021 00:24:08 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id s24sm4658292pfd.118.2021.01.28.00.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 00:24:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/23] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Date: Wed, 27 Jan 2021 22:23:29 -1000 Message-Id: <20210128082331.196801-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128082331.196801-1-richard.henderson@linaro.org> References: <20210128082331.196801-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Signed-off-by: Richard Henderson --- tcg/tci.c | 12 ------------ tcg/tci/tcg-target.c.inc | 16 ---------------- 2 files changed, 28 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/tci.c b/tcg/tci.c index 2ce67a8fd3..32931ea611 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -647,7 +647,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_ri32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; -#if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 = *tb_ptr++; t1 = tci_read_ri32(regs, &tb_ptr); @@ -672,12 +671,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_ri32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 % t2); break; -#elif TCG_TARGET_HAS_div2_i32 - case INDEX_op_div2_i32: - case INDEX_op_divu2_i32: - TODO(); - break; -#endif case INDEX_op_and_i32: t0 = *tb_ptr++; t1 = tci_read_ri32(regs, &tb_ptr); @@ -903,11 +896,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_remu_i64: TODO(); break; -#elif TCG_TARGET_HAS_div2_i64 - case INDEX_op_div2_i64: - case INDEX_op_divu2_i64: - TODO(); - break; #endif case INDEX_op_and_i64: t0 = *tb_ptr++; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index a60fa524a4..842807ff2e 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -71,15 +71,10 @@ static const TCGTargetOpDef tcg_target_op_defs[] = { { INDEX_op_add_i32, { R, RI, RI } }, { INDEX_op_sub_i32, { R, RI, RI } }, { INDEX_op_mul_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i32 { INDEX_op_div_i32, { R, R, R } }, { INDEX_op_divu_i32, { R, R, R } }, { INDEX_op_rem_i32, { R, R, R } }, { INDEX_op_remu_i32, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i32 - { INDEX_op_div2_i32, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i32, { R, R, "0", "1", R } }, -#endif /* TODO: Does R, RI, RI result in faster code than R, R, RI? If both operands are constants, we can optimize. */ { INDEX_op_and_i32, { R, RI, RI } }, @@ -156,9 +151,6 @@ static const TCGTargetOpDef tcg_target_op_defs[] = { { INDEX_op_divu_i64, { R, R, R } }, { INDEX_op_rem_i64, { R, R, R } }, { INDEX_op_remu_i64, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i64 - { INDEX_op_div2_i64, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i64, { R, R, "0", "1", R } }, #endif { INDEX_op_and_i64, { R, RI, RI } }, #if TCG_TARGET_HAS_andc_i64 @@ -705,10 +697,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ TODO(); break; - case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ - case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ - TODO(); - break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); tcg_out_ri64(s, const_args[1], args[1]); @@ -748,10 +736,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_ri32(s, const_args[1], args[1]); tcg_out_ri32(s, const_args[2], args[2]); break; - case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ - case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ - TODO(); - break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: