diff mbox series

[v2,08/22] tcg/mips: Split out target constraints to tcg-target-con-str.h

Message ID 20210115210456.1053477-9-richard.henderson@linaro.org
State Superseded
Headers show
Series tcg: backend constraints cleanup | expand

Commit Message

Richard Henderson Jan. 15, 2021, 9:04 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tcg/mips/tcg-target-con-str.h | 24 ++++++++++++
 tcg/mips/tcg-target.h         |  1 +
 tcg/mips/tcg-target.c.inc     | 72 ++++++++---------------------------
 3 files changed, 41 insertions(+), 56 deletions(-)
 create mode 100644 tcg/mips/tcg-target-con-str.h

-- 
2.25.1

Comments

Peter Maydell Jan. 19, 2021, 2:50 p.m. UTC | #1 
On Fri, 15 Jan 2021 at 21:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  tcg/mips/tcg-target-con-str.h | 24 ++++++++++++

>  tcg/mips/tcg-target.h         |  1 +

>  tcg/mips/tcg-target.c.inc     | 72 ++++++++---------------------------

>  3 files changed, 41 insertions(+), 56 deletions(-)

>  create mode 100644 tcg/mips/tcg-target-con-str.h


> -    case 'Z':

> -        /* We are cheating a bit here, using the fact that the register

> -           ZERO is also the register number 0. Hence there is no need

> -           to check for const_args in each instruction. */

> -        ct->ct |= TCG_CT_CONST_ZERO;


This comment seems like it's worth retaining somewhere.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM
Philippe Mathieu-Daudé Jan. 19, 2021, 10:25 p.m. UTC | #2 
On 1/15/21 10:04 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  tcg/mips/tcg-target-con-str.h | 24 ++++++++++++

>  tcg/mips/tcg-target.h         |  1 +

>  tcg/mips/tcg-target.c.inc     | 72 ++++++++---------------------------

>  3 files changed, 41 insertions(+), 56 deletions(-)

>  create mode 100644 tcg/mips/tcg-target-con-str.h

> 

> diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h

> new file mode 100644

> index 0000000000..e4b2965c72

> --- /dev/null

> +++ b/tcg/mips/tcg-target-con-str.h

> @@ -0,0 +1,24 @@

> +/* SPDX-License-Identifier: MIT */

> +/*

> + * Define MIPS target-specific operand constraints.

> + * Copyright (c) 2021 Linaro

> + */

> +

> +/*

> + * Define constraint letters for register sets:

> + * REGS(letter, register_mask)

> + */

> +REGS('r', ALL_GENERAL_REGS)

> +REGS('L', ALL_QLOAD_REGS)

> +REGS('S', ALL_QSTORE_REGS)

> +

> +/*

> + * Define constraint letters for constants:

> + * CONST(letter, TCG_CT_CONST_* bit set)

> + */

> +CONST('I', TCG_CT_CONST_U16)

> +CONST('J', TCG_CT_CONST_S16)

> +CONST('K', TCG_CT_CONST_P2M1)

> +CONST('N', TCG_CT_CONST_N16)

> +CONST('W', TCG_CT_CONST_WSZ)

> +CONST('Z', TCG_CT_CONST_ZERO)


With the cheating comment Peter requested:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Richard Henderson Jan. 19, 2021, 10:50 p.m. UTC | #3 
On 1/19/21 4:50 AM, Peter Maydell wrote:
> On Fri, 15 Jan 2021 at 21:14, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>>

>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>> ---

>>  tcg/mips/tcg-target-con-str.h | 24 ++++++++++++

>>  tcg/mips/tcg-target.h         |  1 +

>>  tcg/mips/tcg-target.c.inc     | 72 ++++++++---------------------------

>>  3 files changed, 41 insertions(+), 56 deletions(-)

>>  create mode 100644 tcg/mips/tcg-target-con-str.h

> 

>> -    case 'Z':

>> -        /* We are cheating a bit here, using the fact that the register

>> -           ZERO is also the register number 0. Hence there is no need

>> -           to check for const_args in each instruction. */

>> -        ct->ct |= TCG_CT_CONST_ZERO;

> 

> This comment seems like it's worth retaining somewhere.


I moved it to the start of tcg_out_op, which is where we do the operand
checking, and therefore perhaps more usefully placed.


r~
diff mbox series

Patch

diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
new file mode 100644
index 0000000000..e4b2965c72
--- /dev/null
+++ b/tcg/mips/tcg-target-con-str.h
@@ -0,0 +1,24 @@ 
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define MIPS target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_QLOAD_REGS)
+REGS('S', ALL_QSTORE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_U16)
+CONST('J', TCG_CT_CONST_S16)
+CONST('K', TCG_CT_CONST_P2M1)
+CONST('N', TCG_CT_CONST_N16)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c2c32fb38f..d850200855 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -207,5 +207,6 @@  void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 7293169ab2..61e8740012 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -171,67 +171,27 @@  static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_N16  0x1000   /* "Negatable" 16-bit: -32767 - 32767 */
 #define TCG_CT_CONST_WSZ  0x2000   /* word size */
 
+#define ALL_GENERAL_REGS  0xffffffffu
+#define NOA0_REGS         (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+    (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
+#define ALL_QSTORE_REGS \
+    (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS   \
+                   ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3)  \
+                   : (1 << TCG_REG_A1)))
+#else
+#define ALL_QLOAD_REGS   NOA0_REGS
+#define ALL_QSTORE_REGS  NOA0_REGS
+#endif
+
+
 static inline bool is_p2m1(tcg_target_long val)
 {
     return val && ((val + 1) & val) == 0;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch(*ct_str++) {
-    case 'r':
-        ct->regs = 0xffffffff;
-        break;
-    case 'L': /* qemu_ld input arg constraint */
-        ct->regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
-        if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
-        }
-#endif
-        break;
-    case 'S': /* qemu_st constraint */
-        ct->regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
-        if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
-            tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
-        } else {
-            tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
-        }
-#endif
-        break;
-    case 'I':
-        ct->ct |= TCG_CT_CONST_U16;
-        break;
-    case 'J':
-        ct->ct |= TCG_CT_CONST_S16;
-        break;
-    case 'K':
-        ct->ct |= TCG_CT_CONST_P2M1;
-        break;
-    case 'N':
-        ct->ct |= TCG_CT_CONST_N16;
-        break;
-    case 'W':
-        ct->ct |= TCG_CT_CONST_WSZ;
-        break;
-    case 'Z':
-        /* We are cheating a bit here, using the fact that the register
-           ZERO is also the register number 0. Hence there is no need
-           to check for const_args in each instruction. */
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
                                          const TCGArgConstraint *arg_ct)