From patchwork Fri Jan 15 21:04:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363782 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp213657jap; Fri, 15 Jan 2021 13:18:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJxXB8k3Inyt1ou8706HLfHY1Fp1/ab99ia1qlOAmyviBml0nbKDvwLwDXMCoXrFaDbZvP1Q X-Received: by 2002:a05:6902:1001:: with SMTP id w1mr15986395ybt.176.1610745508836; Fri, 15 Jan 2021 13:18:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610745508; cv=none; d=google.com; s=arc-20160816; b=p62EbytlOiUXhu9jWNW4QVeFmidMurxDBBOLzGNlBJMChZ0igg5UOVRvUXK91JLAut vtA3nCzoh9Cz0MDO8l4clqjgCCoFmtaWxPzK4fVEhBr5W/Gc9it4/2Pn9MdiqkyNTdCj EqC47gmbe15IZKySqOHfsMSzLrbGohnRma2rejG8ErD8kjnyGGJBS9WMeXcsfE3IFspj s1mPqpr7adkLESHVlUOgVUZX5moL4S+uKO8G5wK83UIAN11LJtw2qNblQ5ZUALWhbSDR Sv1494zkmdOQWDRoX8Kbbu7w8D0BfkCdVfmpox3CWb+krlsmvLUFLIV4V51PhxwrDgij SBeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=D0+5g8TiaR28cD6Vtw+7Y+J9UW7518EoLSRnQBlNcvo=; b=H5glEeX3jqEI+recdW19W/9L2EYFnzDZg/uoFiKWFLk7ChjURo67pmfRugFUjOEHcB vma/UZrGP6zwVGfQ1mclDYqTMk/i7ZysUeBKR55Zg1ZLgFrE9b7iQZC0TH5E4Uy18lXx 6cCMmQ1CfY0LTt5A4pyXIswpLXe7+9SQXg/ifc1IxEM8k7KUT7I899/Xm2lTGTUDCzzf t9NUP7nH9WEY1rxJWq1YXOnlGodtKrBFFg5HWV5zvfuIny7slXMsC886ItbP2FTEc3Fg +UmP+t5CGD3DYbKrM2dJAekC3Ub6jlU5OxREg2A7lUId6NDZ55IIu5nZ3dzosj9ndqeA Z+4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bY8B1hFG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o13si8227225ybp.52.2021.01.15.13.18.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Jan 2021 13:18:28 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bY8B1hFG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l0WUG-0001cA-AO for patch@linaro.org; Fri, 15 Jan 2021 16:18:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0WHd-00043M-HP for qemu-devel@nongnu.org; Fri, 15 Jan 2021 16:05:25 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:33868) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0WHb-0004HW-Gt for qemu-devel@nongnu.org; Fri, 15 Jan 2021 16:05:25 -0500 Received: by mail-pl1-x62a.google.com with SMTP id t6so5344426plq.1 for ; Fri, 15 Jan 2021 13:05:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=D0+5g8TiaR28cD6Vtw+7Y+J9UW7518EoLSRnQBlNcvo=; b=bY8B1hFGszJcL3qJEKfqyIy3q3udNdGOkwBKVSUGHw7J3D6oKXcACaSl4RiCuZt14t vJCT7py+7i1YAACaF/VCk9/7R4OrJe6LiGDEU87Y2nGKI5EWDFVzWwuuf8v4j30mQBy9 WTxRFsjPFDJfQT2zXlY5IjbgJWV74gppN+hhqKvMRwrCCkzjHRhj+y3SPiqBaBWhyFJd arT5UhdxEDm9R1rtlI5+uOyFgpML+n0T+TKyHsz5eBRfGp6ATyH9p8fxVCwp8C4CSuN+ 9YtjdDM1pOLgeeFv/aP2tcR4K0y/QIRNp1zmCkO9eSzIgcLCufuhFr0VeRnIslE07mRw X5lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D0+5g8TiaR28cD6Vtw+7Y+J9UW7518EoLSRnQBlNcvo=; b=IK9uJM+YN7r3MQFUnyPn4/cO8Z+A4x2H63+aQsfGujYTI7i5Gqw2RrnWPqc2wHCptk d12eLVEq+9se93mriZcOS94MXKMef++uNOgZTqKhjLdmBWlpIkUuUagdBuIh7PPuLhB1 GNL/YLE9+SPRZ3Uy4tz1Zp4Bl+MDqzQuZkRRidP/x9NliryHnMfEjw/e87O8jptXIIb5 4RaQoWOOx8G+TJp+ANi/Cg1fefa7lcfNKojftVSdB5s3oAmp1qyZsuPoPPXswYMgAq4b O3e4+UMdulTBChh0EACY5GTieN8fOl9KabtRVmg5AXLrGdf8M0SNHrme/I0nm8mryqje Beeg== X-Gm-Message-State: AOAM533O9cahR7uhR9EeIxxJ7sLB0A+zWFdkCww4zldKA51IQLS8rXjs gBVbEeQFfml+AS+0HICJLXMfLxgm8flR0sJo X-Received: by 2002:a17:902:b116:b029:dc:c93:1d6b with SMTP id q22-20020a170902b116b02900dc0c931d6bmr14317721plr.22.1610744722077; Fri, 15 Jan 2021 13:05:22 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id h15sm8920221pfo.71.2021.01.15.13.05.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 13:05:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 16/22] tcg/mips: Split out constraint sets to tcg-target-con-set.h Date: Fri, 15 Jan 2021 11:04:50 -1000 Message-Id: <20210115210456.1053477-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115210456.1053477-1-richard.henderson@linaro.org> References: <20210115210456.1053477-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 36 +++++++++++++ tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 96 +++++++++++------------------------ 3 files changed, 66 insertions(+), 67 deletions(-) create mode 100644 tcg/mips/tcg-target-con-set.h -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h new file mode 100644 index 0000000000..fe3e868a2f --- /dev/null +++ b/tcg/mips/tcg-target-con-set.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define MIPS target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I2(SZ, S) +C_O0_I3(SZ, S, S) +C_O0_I3(SZ, SZ, S) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O0_I4(SZ, SZ, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rJ) +C_O1_I2(r, r, rWZ) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, 0) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c2c32fb38f..e520a9d6e3 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -207,5 +207,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_CON_SET_H #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 61e8740012..c93ddbe6b1 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2107,52 +2107,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } }; - static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } }; - static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } }; - static const TCGTargetOpDef SZ_SZ_S - = { .args_ct_str = { "SZ", "SZ", "S" } }; - static const TCGTargetOpDef SZ_SZ_S_S - = { .args_ct_str = { "SZ", "SZ", "S", "S" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_rIK - = { .args_ct_str = { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_rWZ - = { .args_ct_str = { "r", "r", "rWZ" } }; - static const TCGTargetOpDef r_r_r_r - = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } }; - static const TCGTargetOpDef movc_r6 - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2185,7 +2144,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2194,14 +2153,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_rJ; + return C_O1_I2(r, r, rJ); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: case INDEX_op_muluh_i32: @@ -2220,20 +2179,20 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_remu_i64: case INDEX_op_nor_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_muls2_i32: case INDEX_op_mulu2_i32: case INDEX_op_muls2_i64: case INDEX_op_mulu2_i64: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); case INDEX_op_or_i32: case INDEX_op_xor_i32: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: @@ -2244,44 +2203,47 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sar_i64: case INDEX_op_rotr_i64: case INDEX_op_rotl_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_clz_i32: case INDEX_op_clz_i64: - return &r_r_rWZ; + return C_O1_I2(r, r, rWZ); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return use_mips32r6_instructions ? &movc_r6 : &movc; - + return (use_mips32r6_instructions + ? C_O1_I4(r, rZ, rZ, rZ, rZ) + : C_O1_I4(r, rZ, rZ, rZ, 0)); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rN, rN); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(rZ, rZ, rZ, rZ); case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &SZ_S : &SZ_S_S); + ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &SZ_S - : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S); + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) + : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) + : C_O0_I4(SZ, SZ, S, S)); default: - return NULL; + g_assert_not_reached(); } }