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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id u12sm2010pfh.98.2021.01.05.09.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 09:20:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/43] util: Extract flush_icache_range to cacheflush.c Date: Tue, 5 Jan 2021 07:19:09 -1000 Message-Id: <20210105171950.415486-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210105171950.415486-1-richard.henderson@linaro.org> References: <20210105171950.415486-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joelle van Dyne , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/qemu/cacheflush.h | 24 +++++++++++++ tcg/aarch64/tcg-target.h | 5 --- tcg/arm/tcg-target.h | 5 --- tcg/i386/tcg-target.h | 4 --- tcg/mips/tcg-target.h | 11 ------ tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 5 --- tcg/s390/tcg-target.h | 4 --- tcg/sparc/tcg-target.h | 8 ----- tcg/tci/tcg-target.h | 4 --- softmmu/physmem.c | 1 + tcg/tcg.c | 1 + util/cacheflush.c | 71 +++++++++++++++++++++++++++++++++++++++ tcg/ppc/tcg-target.c.inc | 22 ------------ MAINTAINERS | 2 ++ util/meson.build | 2 +- 16 files changed, 100 insertions(+), 70 deletions(-) create mode 100644 include/qemu/cacheflush.h create mode 100644 util/cacheflush.c -- 2.25.1 diff --git a/include/qemu/cacheflush.h b/include/qemu/cacheflush.h new file mode 100644 index 0000000000..58ae488491 --- /dev/null +++ b/include/qemu/cacheflush.h @@ -0,0 +1,24 @@ +/* + * Flush the host cpu caches. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_CACHEFLUSH_H +#define QEMU_CACHEFLUSH_H + +#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) + +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + /* icache is coherent and does not require flushing. */ +} + +#else + +void flush_icache_range(uintptr_t start, uintptr_t stop); + +#endif + +#endif /* QEMU_CACHEFLUSH_H */ diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index d1159d80c6..108a1fa969 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -149,11 +149,6 @@ typedef enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *)start, (char *)stop); -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 1e132afa75..1e18fefd0e 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -135,11 +135,6 @@ enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *) start, (char *) stop); -} - /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index abe8636f0d..f3836a4d0c 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -210,10 +210,6 @@ extern bool have_movbe; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index b04c12d317..624248b81e 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -199,20 +199,9 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif -#ifdef __OpenBSD__ -#include -#else -#include -#endif - #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - cacheflush ((void *)start, stop-start, ICACHE); -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 7ff46b3d6d..301173c97e 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -176,7 +176,6 @@ extern bool have_vsx; #define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 -void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ccda7b83c4..888288d54c 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -160,11 +160,6 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i64 1 #endif -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *)start, (char *)stop); -} - /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 7e7396caf2..69576f4a9a 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -146,10 +146,6 @@ enum { TCG_AREG0 = TCG_REG_R10, }; -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index f2989b3b45..9dce305253 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -169,14 +169,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - uintptr_t p; - for (p = start & -8; p < ((stop + 7) & -8); p += 8) { - __asm__ __volatile__("flush\t%0" : : "r" (p)); - } -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 7192d5319e..e8277caee2 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -192,10 +192,6 @@ void tci_disas(uint8_t opc); #define HAVE_TCG_QEMU_TB_EXEC -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. We prefer consistency across hosts on this. */ diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 2cd1de4a2c..c595266b9f 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "qemu/cutils.h" +#include "qemu/cacheflush.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/target_page.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index df2857dc88..9bdc450196 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -35,6 +35,7 @@ #include "qemu/host-utils.h" #include "qemu/qemu-print.h" #include "qemu/timer.h" +#include "qemu/cacheflush.h" /* Note: the long term plan is to reduce the dependencies on the QEMU CPU definitions. Currently they are used for qemu_ld/st diff --git a/util/cacheflush.c b/util/cacheflush.c new file mode 100644 index 0000000000..2881832a38 --- /dev/null +++ b/util/cacheflush.c @@ -0,0 +1,71 @@ +/* + * Flush the host cpu caches. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/cacheflush.h" + + +#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) + +/* Caches are coherent and do not require flushing; symbol inline. */ + +#elif defined(__mips__) + +#ifdef __OpenBSD__ +#include +#else +#include +#endif + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + cacheflush((void *)start, stop - start, ICACHE); +} + +#elif defined(__powerpc__) + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + uintptr_t p, start1, stop1; + size_t dsize = qemu_dcache_linesize; + size_t isize = qemu_icache_linesize; + + start1 = start & ~(dsize - 1); + stop1 = (stop + dsize - 1) & ~(dsize - 1); + for (p = start1; p < stop1; p += dsize) { + asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + + start &= start & ~(isize - 1); + stop1 = (stop + isize - 1) & ~(isize - 1); + for (p = start1; p < stop1; p += isize) { + asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + asm volatile ("isync" : : : "memory"); +} + +#elif defined(__sparc__) + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + uintptr_t p; + + for (p = start & -8; p < ((stop + 7) & -8); p += 8) { + __asm__ __volatile__("flush\t%0" : : "r" (p)); + } +} + +#else + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + __builtin___clear_cache((char *)start, (char *)stop); +} + +#endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 18ee989f95..0d068ec8ab 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3863,25 +3863,3 @@ void tcg_register_jit(void *buf, size_t buf_size) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } #endif /* __ELF__ */ - -void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - uintptr_t p, start1, stop1; - size_t dsize = qemu_dcache_linesize; - size_t isize = qemu_icache_linesize; - - start1 = start & ~(dsize - 1); - stop1 = (stop + dsize - 1) & ~(dsize - 1); - for (p = start1; p < stop1; p += dsize) { - asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); - } - asm volatile ("sync" : : : "memory"); - - start &= start & ~(isize - 1); - stop1 = (stop + isize - 1) & ~(isize - 1); - for (p = start1; p < stop1; p += isize) { - asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); - } - asm volatile ("sync" : : : "memory"); - asm volatile ("isync" : : : "memory"); -} diff --git a/MAINTAINERS b/MAINTAINERS index 42fedf91e7..478bea667c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -119,6 +119,8 @@ F: softmmu/cpus.c F: cpus-common.c F: accel/tcg/ F: accel/stubs/tcg-stub.c +F: util/cacheinfo.c +F: util/cacheflush.c F: scripts/decodetree.py F: docs/devel/decodetree.rst F: include/exec/cpu*.h diff --git a/util/meson.build b/util/meson.build index f359af0d46..a3dfc0f966 100644 --- a/util/meson.build +++ b/util/meson.build @@ -21,7 +21,7 @@ util_ss.add(files('envlist.c', 'path.c', 'module.c')) util_ss.add(files('host-utils.c')) util_ss.add(files('bitmap.c', 'bitops.c')) util_ss.add(files('fifo8.c')) -util_ss.add(files('cacheinfo.c')) +util_ss.add(files('cacheinfo.c', 'cacheflush.c')) util_ss.add(files('error.c', 'qemu-error.c')) util_ss.add(files('qemu-print.c')) util_ss.add(files('id.c'))