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[209.51.188.17]) by mx.google.com with ESMTPS id p71si354673ybg.346.2021.01.05.08.54.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Jan 2021 08:54:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from localhost ([::1]:59926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kwpbG-00089Y-9w for patch@linaro.org; Tue, 05 Jan 2021 11:54:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwpam-00089J-4C for qemu-devel@nongnu.org; Tue, 05 Jan 2021 11:53:56 -0500 Received: from mga11.intel.com ([192.55.52.93]:21248) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwpaj-00012W-LJ for qemu-devel@nongnu.org; Tue, 05 Jan 2021 11:53:55 -0500 IronPort-SDR: Jm0F1gwMqf9ZuckuBdXA7YHbpgEKXzwzSpUlROWccr0bg08zHDuN/F0wmvZM13iqIPGULNT4q4 Sfv9VHKy2l2g== X-IronPort-AV: E=McAfee;i="6000,8403,9855"; a="173629492" X-IronPort-AV: E=Sophos;i="5.78,477,1599548400"; d="scan'208";a="173629492" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2021 08:53:50 -0800 IronPort-SDR: Wgs42zxH37SYT9IKqYxff4sjVLkaXyQfjhgcf+c3Ue3bVF+WfaR7vbP2l0GsCz/tf1iAiX4JHg RuX4Omezx1sg== X-IronPort-AV: E=Sophos;i="5.78,477,1599548400"; d="scan'208";a="346337929" Received: from tgeddam-mobl.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.140.57]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2021 08:53:49 -0800 From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 01/32] Temp: Add the PCI_EXT_ID_DVSEC definition to the qemu pci_regs.h copy. Date: Tue, 5 Jan 2021 08:52:52 -0800 Message-Id: <20210105165323.783725-2-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210105165323.783725-1-ben.widawsky@intel.com> References: <20210105165323.783725-1-ben.widawsky@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.93; envelope-from=ben.widawsky@intel.com; helo=mga11.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Ben Widawsky , "Michael S. Tsirkin" , Vishal Verma , Chris Browy , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jonathan Cameron , Prashant V Agarwal , Dan Williams Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jonathan Cameron This hasn't yet been added to the linux kernel tree, so for purposes of this RFC just add it locally. Signed-off-by: Jonathan Cameron Signed-off-by: Ben Widawsky --- include/standard-headers/linux/pci_regs.h | 1 + 1 file changed, 1 insertion(+) -- 2.30.0 diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h index a95d55f9f2..5d0b79b9da 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -723,6 +723,7 @@ #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT