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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 23/23] tcg/aarch64: Use tcg_constant_vec with tcg vec expanders Date: Thu, 17 Dec 2020 08:52:15 -0600 Message-Id: <20201217145215.534637-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to "t1 = -v, t2 = c - v2". This avoids a serial dependency between t1 and t2. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index a6c2d54c4d..c78e809de8 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2511,7 +2511,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t1, t2; + TCGv_vec v0, v1, v2, t1, t2, c1; TCGArg a2; va_start(va, a0); @@ -2543,8 +2543,8 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotlv_vec: t1 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(vece, t1, 8 << vece); - tcg_gen_sub_vec(vece, t1, v2, t1); + c1 = tcg_constant_vec(type, vece, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, c1); /* Right shifts are negative left shifts for AArch64. */ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t1)); @@ -2557,9 +2557,9 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotrv_vec: t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); + c1 = tcg_constant_vec(type, vece, 8 << vece); tcg_gen_neg_vec(vece, t1, v2); - tcg_gen_dupi_vec(vece, t2, 8 << vece); - tcg_gen_add_vec(vece, t2, t1, t2); + tcg_gen_sub_vec(vece, t2, c1, v2); /* Right shifts are negative left shifts for AArch64. */ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t1));