[v2,01/24] target/arm: Fix decode of align in VLDST_single

Message ID	20201208180118.157911-2-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v2 01/24] target/arm: Fix decode of align in VLDST_single Date: Tue, 8 Dec 2020 12:00:55 -0600 Message-Id: <20201208180118.157911-2-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-1-richard.henderson@linaro.org> References: <20201208180118.157911-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: enforce alignment \| expand [v2,00/24] target/arm: enforce alignment [v2,01/24] target/arm: Fix decode of align in VLDST_single [v2,02/24] target/arm: Add ALIGN_MEM to TBFLAG_ANY [v2,03/24] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness [v2,04/24] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 [v2,05/24] target/arm: Fix SCTLR_B test for TCGv_i64 load/store [v2,06/24] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness [v2,07/24] target/arm: Enforce word alignment for LDRD/STRD [v2,08/24] target/arm: Enforce alignment for LDA/LDAH/STL/STLH [v2,09/24] target/arm: Enforce alignment for LDM/STM [v2,10/24] target/arm: Enforce alignment for RFE [v2,11/24] target/arm: Enforce alignment for SRS [v2,12/24] target/arm: Enforce alignment for VLDM/VSTM [v2,13/24] target/arm: Enforce alignment for VLDR/VSTR [v2,14/24] target/arm: Enforce alignment for VLD1 (all lanes) [v2,15/24] target/arm: Enforce alignment for VLDn/VSTn (multiple) [v2,16/24] target/arm: Enforce alignment for VLDn/VSTn (single) [v2,17/24] target/arm: Use finalize_memop for aa64 gpr load/store [v2,18/24] target/arm: Use finalize_memop for aa64 fpr load/store [v2,19/24] target/arm: Enforce alignment for aa64 load-acq/store-rel [v2,20/24] target/arm: Use MemOp for size + endian in aa64 vector ld/st [v2,21/24] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) [v2,22/24] target/arm: Enforce alignment for aa64 vector LDn/STn (single) [v2,23/24] target/arm: Enforce alignment for sve LD1R [v2,24/24] target/arm: Enforce alignment for sve unpredicated LDR/STR

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v2 01/24] target/arm: Fix decode of align in VLDST_single
Date: Tue,  8 Dec 2020 12:00:55 -0600
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Series

target/arm: enforce alignment | expand

Commit Message

Richard Henderson Dec. 8, 2020, 6 p.m. UTC

The encoding of size = 2 and size = 3 had the incorrect decode
for align, overlapping the stride field.  This error was hidden
by what should have been unnecessary masking in translate.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/neon-ls.decode       | 4 ++--
 target/arm/translate-neon.c.inc | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

-- 
2.25.1

diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index c17f5019e3..0a2a0e15db 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -46,7 +46,7 @@  VLD_all_lanes  1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
 
 VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
                vd=%vd_dp size=0 stride=1
-VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
+VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \
                vd=%vd_dp size=1 stride=%imm1_5_p1
-VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
+VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \
                vd=%vd_dp size=2 stride=%imm1_6_p1
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index f6c68e30ab..0e5828744b 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -606,7 +606,7 @@  static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
     switch (nregs) {
     case 1:
         if (((a->align & (1 << a->size)) != 0) ||
-            (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
+            (a->size == 2 && (a->align == 1 || a->align == 2))) {
             return false;
         }
         break;
@@ -621,7 +621,7 @@  static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
         }
         break;
     case 4:
-        if ((a->size == 2) && ((a->align & 3) == 3)) {
+        if (a->size == 2 && a->align == 3) {
             return false;
         }
         break;

[v2,01/24] target/arm: Fix decode of align in VLDST_single

Commit Message

Patch