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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id mn15sm1600297pjb.21.2020.10.27.07.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2020 07:18:31 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module Date: Tue, 27 Oct 2020 22:17:37 +0800 Message-Id: <20201027141740.18336-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201027141740.18336-1-bmeng.cn@gmail.com> References: <20201027141740.18336-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1032.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Atish Patra , Anup Patel , Ivan Griffin Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Previously SYSREG was created as an unimplemented device. Now that we have a simple SYSREG module, connect it. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/Kconfig | 1 + hw/riscv/microchip_pfsoc.c | 9 ++++++--- include/hw/riscv/microchip_pfsoc.h | 2 ++ 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 8f043e38e0..facb0cbacc 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -7,6 +7,7 @@ config MICROCHIP_PFSOC select MCHP_PFSOC_DMC select MCHP_PFSOC_IOSCB select MCHP_PFSOC_MMUART + select MCHP_PFSOC_SYSREG select MSI_NONBROKEN select SIFIVE_CLINT select SIFIVE_PDMA diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 05fb5004a1..69117c6000 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -135,6 +135,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "dma-controller", &s->dma, TYPE_SIFIVE_PDMA); + object_initialize_child(obj, "sysreg", &s->sysreg, + TYPE_MCHP_PFSOC_SYSREG); + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, TYPE_MCHP_PFSOC_DDR_SGMII_PHY); object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, @@ -262,9 +265,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) } /* SYSREG */ - create_unimplemented_device("microchip.pfsoc.sysreg", - memmap[MICROCHIP_PFSOC_SYSREG].base, - memmap[MICROCHIP_PFSOC_SYSREG].size); + sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, + memmap[MICROCHIP_PFSOC_SYSREG].base); /* MPUCFG */ create_unimplemented_device("microchip.pfsoc.mpucfg", diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index a244ae6d39..245c82db61 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -26,6 +26,7 @@ #include "hw/dma/sifive_pdma.h" #include "hw/misc/mchp_pfsoc_dmc.h" #include "hw/misc/mchp_pfsoc_ioscb.h" +#include "hw/misc/mchp_pfsoc_sysreg.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" @@ -47,6 +48,7 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial2; MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; + MchpPfSoCSysregState sysreg; SiFivePDMAState dma; CadenceGEMState gem0; CadenceGEMState gem1;