diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index cc49a35013..9e363d72ee 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -36,25 +36,29 @@
 
 static void ibex_uart_update_irqs(IbexUartState *s)
 {
-    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
+    if (s->uart_intr_state & s->uart_intr_enable &
+        R_INTR_STATE_TX_WATERMARK_MASK) {
         qemu_set_irq(s->tx_watermark, 1);
     } else {
         qemu_set_irq(s->tx_watermark, 0);
     }
 
-    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) {
+    if (s->uart_intr_state & s->uart_intr_enable &
+        R_INTR_STATE_RX_WATERMARK_MASK) {
         qemu_set_irq(s->rx_watermark, 1);
     } else {
         qemu_set_irq(s->rx_watermark, 0);
     }
 
-    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) {
+    if (s->uart_intr_state & s->uart_intr_enable &
+        R_INTR_STATE_TX_EMPTY_MASK) {
         qemu_set_irq(s->tx_empty, 1);
     } else {
         qemu_set_irq(s->tx_empty, 0);
     }
 
-    if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) {
+    if (s->uart_intr_state & s->uart_intr_enable &
+        R_INTR_STATE_RX_OVERFLOW_MASK) {
         qemu_set_irq(s->rx_overflow, 1);
     } else {
         qemu_set_irq(s->rx_overflow, 0);
diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
index e8da933378..e45f5bf117 100644
--- a/hw/char/omap_uart.c
+++ b/hw/char/omap_uart.c
@@ -168,7 +168,8 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
     struct omap_uart_s *s = omap_uart_init(base, irq,
                     fclk, iclk, txdma, rxdma, label, chr);
 
-    memory_region_init_io(&s->iomem, NULL, &omap_uart_ops, s, "omap.uart", 0x100);
+    memory_region_init_io(&s->iomem, NULL, &omap_uart_ops, s,
+                          "omap.uart", 0x100);
 
     s->ta = ta;
 
diff --git a/hw/char/parallel.c b/hw/char/parallel.c
index 8b418abf71..b1f6a0572b 100644
--- a/hw/char/parallel.c
+++ b/hw/char/parallel.c
@@ -73,7 +73,8 @@
 #define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
 #define PARA_CTR_STROBE	0x01	/* Strobe complement */
 
-#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
+#define PARA_CTR_SIGNAL (PARA_CTR_SELECT | PARA_CTR_INIT | PARA_CTR_AUTOLF | \
+                         PARA_CTR_STROBE)
 
 typedef struct ParallelState {
     MemoryRegion iomem;
@@ -294,7 +295,8 @@ static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
     case PARA_REG_STS:
         ret = s->status;
         s->irq_pending = 0;
-        if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
+        if ((s->status & PARA_STS_BUSY) == 0 &&
+            (s->control & PARA_CTR_STROBE) == 0) {
             /* XXX Fixme: wait 5 microseconds */
             if (s->status & PARA_STS_ACK)
                 s->status &= ~PARA_STS_ACK;
@@ -397,7 +399,8 @@ parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
     struct ParallelIOArg ioarg = {
         .buffer = &eppdata, .count = sizeof(eppdata)
     };
-    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
+    if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
+        (PARA_CTR_DIR | PARA_CTR_INIT)) {
         /* Controls not correct for EPP data cycle, so do nothing */
         pdebug("re%04x s\n", eppdata);
         return eppdata;
@@ -425,7 +428,8 @@ parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
     struct ParallelIOArg ioarg = {
         .buffer = &eppdata, .count = sizeof(eppdata)
     };
-    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
+    if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
+        (PARA_CTR_DIR | PARA_CTR_INIT)) {
         /* Controls not correct for EPP data cycle, so do nothing */
         pdebug("re%08x s\n", eppdata);
         return eppdata;
diff --git a/hw/char/serial.c b/hw/char/serial.c
index 97f71879ff..cbc662e077 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -86,7 +86,10 @@
 #define UART_LSR_DR	0x01	/* Receiver data ready */
 #define UART_LSR_INT_ANY 0x1E	/* Any of the lsr-interrupt-triggering status bits */
 
-/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
+/*
+ * Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the
+ * byte-count for each ITL is higher.
+ */
 
 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
@@ -195,10 +198,14 @@ static void serial_update_msl(SerialState *s)
 
     omsr = s->msr;
 
-    s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
-    s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
-    s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
-    s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
+    s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS :
+              s->msr & ~UART_MSR_CTS;
+    s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR :
+              s->msr & ~UART_MSR_DSR;
+    s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD :
+              s->msr & ~UART_MSR_DCD;
+    s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI :
+              s->msr & ~UART_MSR_RI;
 
     if (s->msr != omsr) {
          /* Set delta bits */
@@ -209,8 +216,11 @@ static void serial_update_msl(SerialState *s)
          serial_update_irq(s);
     }
 
-    /* The real 16550A apparently has a 250ns response latency to line status changes.
-       We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
+    /*
+     * The real 16550A apparently has a 250ns response latency to line status
+     * changes. We'll be lazy and poll only every 10ms, and only poll it at all
+     * if MSI interrupts are turned on
+     */
 
     if (s->poll_msl) {
         timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
@@ -369,8 +379,10 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
         } else {
             uint8_t changed = (s->ier ^ val) & 0x0f;
             s->ier = val & 0x0f;
-            /* If the backend device is a real serial port, turn polling of the modem
-             * status lines on physical port on or off depending on UART_IER_MSI state.
+            /*
+             * If the backend device is a real serial port, turn polling of the
+             * modem status lines on physical port on or off depending on
+             * UART_IER_MSI state.
              */
             if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {
                 if (s->ier & UART_IER_MSI) {
@@ -386,9 +398,9 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
              * if LSR.THRE=1, even if it had been masked before by reading IIR.
              * This is not in the datasheet, but Windows relies on it.  It is
              * unclear if THRE has to be resampled every time THRI becomes
-             * 1, or only on the rising edge.  Bochs does the latter, and Windows
-             * always toggles IER to all zeroes and back to all ones, so do the
-             * same.
+             * 1, or only on the rising edge.  Bochs does the latter, and
+             * Windows always toggles IER to all zeroes and back to all ones,
+             * so do the same.
              *
              * If IER.THRI is zero, thr_ipending is not used.  Set it to zero
              * so that the thr_ipending subsection is not migrated.
@@ -407,7 +419,10 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
         }
         break;
     case 2:
-        /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
+        /*
+         * Did the enable/disable flag change? If so, make sure FIFOs get
+         * flushed
+         */
         if ((val ^ s->fcr) & UART_FCR_FE) {
             val |= UART_FCR_XFR | UART_FCR_RFR;
         }
@@ -452,9 +467,14 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
 
             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
                 serial_update_tiocm(s);
-                /* Update the modem status after a one-character-send wait-time, since there may be a response
-                   from the device/computer at the other end of the serial line */
-                timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
+                /*
+                 * Update the modem status after a one-character-send wait-time,
+                 * since there may be a response from the device/computer at the
+                 * other end of the serial line
+                 */
+                timer_mod(s->modem_status_poll,
+                          qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+                          s->char_transmit_time);
             }
         }
         break;
@@ -584,7 +604,10 @@ static void serial_receive_break(SerialState *s)
     serial_update_irq(s);
 }
 
-/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
+/*
+ * There's data in recv_fifo and s->rbr has not been read for 4 char transmit
+ * times
+ */
 static void fifo_timeout_int (void *opaque) {
     SerialState *s = opaque;
     if (s->recv_fifo.num) {
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
index cf08ef9728..5921377c51 100644
--- a/hw/char/virtio-serial-bus.c
+++ b/hw/char/virtio-serial-bus.c
@@ -1085,7 +1085,8 @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp)
         vser->ovqs[i] = virtio_add_queue(vdev, 128, handle_output);
     }
 
-    vser->ports_map = g_malloc0((DIV_ROUND_UP(vser->serial.max_virtserial_ports, 32))
+    vser->ports_map = g_malloc0((DIV_ROUND_UP(vser->serial.max_virtserial_ports,
+                                              32))
         * sizeof(vser->ports_map[0]));
     /*
      * Reserve location 0 for a console port for backward compat
