diff --git a/hw/pci/msi.c b/hw/pci/msi.c
index 47d2b0f33c..7adea829cb 100644
--- a/hw/pci/msi.c
+++ b/hw/pci/msi.c
@@ -47,7 +47,8 @@
  * supporting such, so removing the capability is not required, and
  * it seems cleaner to have a given device look the same for all boards.
  *
- * TODO: some existing controllers violate the above rule. Identify and fix them.
+ * TODO: some existing controllers violate the above rule. Identify and fix
+ * them.
  */
 bool msi_nonbroken;
 
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 67e34f34d6..7498af09c2 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -334,11 +334,11 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
 
     msix_mask_all(dev, nentries);
 
-    memory_region_init_io(&dev->msix_table_mmio, OBJECT(dev), &msix_table_mmio_ops, dev,
-                          "msix-table", table_size);
+    memory_region_init_io(&dev->msix_table_mmio, OBJECT(dev),
+                          &msix_table_mmio_ops, dev, "msix-table", table_size);
     memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio);
-    memory_region_init_io(&dev->msix_pba_mmio, OBJECT(dev), &msix_pba_mmio_ops, dev,
-                          "msix-pba", pba_size);
+    memory_region_init_io(&dev->msix_pba_mmio, OBJECT(dev),
+                          &msix_pba_mmio_ops, dev, "msix-pba", pba_size);
     memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
 
     return 0;
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 100c9381c2..96d1b88d79 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1391,7 +1391,8 @@ uint32_t pci_default_read_config(PCIDevice *d,
     return le32_to_cpu(val);
 }
 
-void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
+void pci_default_write_config(PCIDevice *d, uint32_t addr,
+                              uint32_t val_in, int l)
 {
     int i, was_irq_disabled = pci_irq_disabled(d);
     uint32_t val = val_in;
@@ -1691,9 +1692,11 @@ static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
         } else {
             region->value->type = g_strdup("memory");
             region->value->has_prefetch = true;
-            region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
+            region->value->prefetch = !!(r->type &
+                                         PCI_BASE_ADDRESS_MEM_PREFETCH);
             region->value->has_mem_type_64 = true;
-            region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
+            region->value->mem_type_64 = !!(r->type &
+                                            PCI_BASE_ADDRESS_MEM_TYPE_64);
         }
 
         region->value->bar = i;
@@ -1738,10 +1741,13 @@ static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
     range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
 
     if (dev->config[PCI_SECONDARY_BUS] != 0) {
-        PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
+        PCIBus *child_bus =
+                   pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
         if (child_bus) {
             info->has_devices = true;
-            info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
+            info->devices =
+                qmp_query_pci_devices(child_bus,
+                                      dev->config[PCI_SECONDARY_BUS]);
         }
     }
 
@@ -1986,9 +1992,9 @@ PCIDevice *pci_vga_init(PCIBus *bus)
 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
 {
     return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
-             PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
-        dev->config[PCI_SECONDARY_BUS] <= bus_num &&
-        bus_num <= dev->config[PCI_SUBORDINATE_BUS];
+             PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */
+             && dev->config[PCI_SECONDARY_BUS] <= bus_num
+             && bus_num <= dev->config[PCI_SUBORDINATE_BUS];
 }
 
 /* Whether a given bus number is in a range of a root bus */
@@ -2050,7 +2056,8 @@ static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
 }
 
 void pci_for_each_bus_depth_first(PCIBus *bus,
-                                  void *(*begin)(PCIBus *bus, void *parent_state),
+                                  void *(*begin)(PCIBus *bus,
+                                  void *parent_state),
                                   void (*end)(PCIBus *bus, void *state),
                                   void *parent_state)
 {
@@ -2363,7 +2370,8 @@ static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
     if (vmsd) {
         snprintf(name, sizeof(name), "%s.rom", vmsd->name);
     } else {
-        snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
+        snprintf(name, sizeof(name), "%s.rom",
+                 object_get_typename(OBJECT(pdev)));
     }
     pdev->has_rom = true;
     memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
@@ -2729,7 +2737,8 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
 
     if (pc->is_bridge) {
         pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
-        pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
+        pcibus_t limit = pci_bridge_get_limit(dev,
+                                              PCI_BASE_ADDRESS_MEM_PREFETCH);
 
         base = MAX(base, 0x1ULL << 32);
 
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 3789c17edc..4124f3c156 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -379,7 +379,8 @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
     sec_bus->parent_dev = dev;
     sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
     sec_bus->address_space_mem = &br->address_space_mem;
-    memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
+    memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci",
+                       UINT64_MAX);
     sec_bus->address_space_io = &br->address_space_io;
     memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
                        4 * GiB);
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 5b48bae0f6..344d013c95 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -644,10 +644,10 @@ void pcie_cap_slot_write_config(PCIDevice *dev,
     if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
         /*
          * Guests tend to clears all bits during init.
-         * If they clear bits that weren't set this is racy and will lose events:
-         * not a big problem for manual button presses, but a problem for us.
-         * As a work-around, detect this and revert status to what it was
-         * before the write.
+         * If they clear bits that weren't set this is racy and will lose
+         * events: not a big problem for manual button presses, but a problem
+         * for us. As a work-around, detect this and revert status to what it
+         * was before the write.
          *
          * Note: in theory this can be detected as a duplicate button press
          * which cancels the previous press. Does not seem to happen in
@@ -658,7 +658,8 @@ void pcie_cap_slot_write_config(PCIDevice *dev,
                           PCI_EXP_SLTSTA_CC)
 
         if (val & ~old_slt_sta & PCIE_SLOT_EVENTS) {
-            sltsta = (sltsta & ~PCIE_SLOT_EVENTS) | (old_slt_sta & PCIE_SLOT_EVENTS);
+            sltsta = (sltsta & ~PCIE_SLOT_EVENTS) |
+                     (old_slt_sta & PCIE_SLOT_EVENTS);
             pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
         }
         hotplug_event_clear(dev);
diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index 3534006f99..9a3f09fb25 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -79,8 +79,8 @@ static void pcie_host_init(Object *obj)
     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
 
     e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
-    memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e, "pcie-mmcfg-mmio",
-                          PCIE_MMCFG_SIZE_MAX);
+    memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e,
+                          "pcie-mmcfg-mmio", PCIE_MMCFG_SIZE_MAX);
 }
 
 void pcie_host_mmcfg_unmap(PCIExpressHost *e)
