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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id u63sm622327wmb.13.2020.10.15.15.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2020 15:48:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Victor Kamensky Subject: [RFC PATCH v2 3/4] target/mips: Make the number of TLB entries a CPU property Date: Fri, 16 Oct 2020 00:47:45 +0200 Message-Id: <20201015224746.540027-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201015224746.540027-1-f4bug@amsat.org> References: <20201015224746.540027-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Khem Raj , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Richard Purdie , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Allow selecting the number of TLB entries from a preset array. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 1 + target/mips/cpu.c | 8 +++++++- target/mips/translate.c | 26 ++++++++++++++++++++++++-- 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index c2b2e79c515..34f82c6e842 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -29,6 +29,7 @@ struct mips_def_t { int32_t CP0_PRid; int32_t CP0_Config0; int32_t CP0_Config1; + const unsigned *CP0_Config1_MMU_preset; int32_t CP0_Config2; int32_t CP0_Config3; int32_t CP0_Config4; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 117c748345e..da31831368b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -26,7 +26,7 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "exec/exec-all.h" - +#include "hw/qdev-properties.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -183,6 +183,11 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) return oc; } +static Property mips_cpu_properties[] = { + DEFINE_PROP_UINT8("tlb-entries", MIPSCPU, env.tlb_entries, 0), + DEFINE_PROP_END_OF_LIST() +}; + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); @@ -192,6 +197,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); + device_class_set_props(dc, mips_cpu_properties); cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; diff --git a/target/mips/translate.c b/target/mips/translate.c index 698bcee8915..f5815160fb6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -39,6 +39,7 @@ #include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" +#include "qapi/error.h" #define MIPS_DEBUG_DISAS 0 @@ -31318,9 +31319,30 @@ void mips_tcg_init(void) static bool init_tlb_entries(CPUMIPSState *env, Error **errp) { - env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6); + const unsigned *preset = env->cpu_model->CP0_Config1_MMU_preset; + bool valid = false; - return true; + if (!env->tlb_entries) { + env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, + CP0C1_MMU, 6); + return true; + } + if (!preset) { + error_setg(errp, "Property 'tlb-entries' not modifiable for this CPU"); + return false; + } + while (!valid && *preset) { + if (*preset == env->tlb_entries) { + valid = true; + break; + } + preset++; + } + if (!valid) { + error_setg(errp, "Invalid value '%u' for property 'tlb-entries'", + env->tlb_entries); + } + return valid; } bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp)