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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id j134sm619347wmj.7.2020.10.15.15.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2020 15:47:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Victor Kamensky Subject: [RFC PATCH v2 2/4] target/mips: Store number of TLB entries in CPUMIPSState Date: Fri, 16 Oct 2020 00:47:44 +0200 Message-Id: <20201015224746.540027-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201015224746.540027-1-f4bug@amsat.org> References: <20201015224746.540027-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Khem Raj , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Richard Purdie , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" As we want to make the number of TLB entries configurable, store it in CPUMIPSState. Introduce the init_tlb_entries() helper which initializes it from the CP0C1_MMU config content. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 + target/mips/translate.c | 13 ++++++++++++- target/mips/translate_init.c.inc | 2 +- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7cf7f5239f7..b84e9a8fcae 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1140,6 +1140,7 @@ struct CPUMIPSState { #endif const mips_def_t *cpu_model; + uint8_t tlb_entries; void *irq[8]; QEMUTimer *timer; /* Internal timer */ struct MIPSITUState *itu; diff --git a/target/mips/translate.c b/target/mips/translate.c index 4c9b6216321..698bcee8915 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31316,8 +31316,18 @@ void mips_tcg_init(void) #include "translate_init.c.inc" +static bool init_tlb_entries(CPUMIPSState *env, Error **errp) +{ + env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6); + + return true; +} + bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp) { + if (!init_tlb_entries(env, errp)) { + return false; + } env->exception_base = (int32_t)0xBFC00000; #ifndef CONFIG_USER_ONLY @@ -31357,7 +31367,8 @@ void cpu_state_reset(CPUMIPSState *env) #ifdef TARGET_WORDS_BIGENDIAN env->CP0_Config0 |= (1 << CP0C0_BE); #endif - env->CP0_Config1 = env->cpu_model->CP0_Config1; + env->CP0_Config1 = deposit32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6, + env->tlb_entries - 1); env->CP0_Config2 = env->cpu_model->CP0_Config2; env->CP0_Config3 = env->cpu_model->CP0_Config3; env->CP0_Config4 = env->cpu_model->CP0_Config4; diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index 637caccd890..a426463c434 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -946,7 +946,7 @@ static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) { - env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); + env->tlb->nb_tlb = env->tlb_entries; env->tlb->map_address = &r4k_map_address; env->tlb->helper_tlbwi = r4k_helper_tlbwi; env->tlb->helper_tlbwr = r4k_helper_tlbwr;