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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id n9sm22111984wrq.72.2020.10.11.12.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2020 12:49:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 1/4] hw: Replace magic value by PCI_NUM_PINS definition Date: Sun, 11 Oct 2020 21:49:15 +0200 Message-Id: <20201011194918.3219195-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201011194918.3219195-1-f4bug@amsat.org> References: <20201011194918.3219195-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Aleksandar Rikalo , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , qemu-arm@nongnu.org, Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Use self-explicit PCI_NUM_PINS definition instead of magic value. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 4 ++-- hw/mips/gt64xxx_pci.c | 2 +- hw/pci-host/versatile.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e465a988d68..ddad9621f79 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1117,11 +1117,11 @@ static void create_pcie_irq_map(const VirtMachineState *vms, int first_irq, const char *nodename) { int devfn, pin; - uint32_t full_irq_map[4 * 4 * 10] = { 0 }; + uint32_t full_irq_map[4 * PCI_NUM_PINS * 10] = { 0 }; uint32_t *irq_map = full_irq_map; for (devfn = 0; devfn <= 0x18; devfn += 0x8) { - for (pin = 0; pin < 4; pin++) { + for (pin = 0; pin < PCI_NUM_PINS; pin++) { int irq_type = GIC_FDT_IRQ_TYPE_SPI; int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index e091bc4ed55..ff1a35755f6 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1018,7 +1018,7 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; - for (i = 0; i < 4; i++) { + for (i = 0; i < PCI_NUM_PINS; i++) { if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { pic_level |= pci_irq_levels[i]; } diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c index 3553277f941..b4951023f4e 100644 --- a/hw/pci-host/versatile.c +++ b/hw/pci-host/versatile.c @@ -75,7 +75,7 @@ enum { struct PCIVPBState { PCIHostState parent_obj; - qemu_irq irq[4]; + qemu_irq irq[PCI_NUM_PINS]; MemoryRegion controlregs; MemoryRegion mem_config; MemoryRegion mem_config2; @@ -412,7 +412,7 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp) object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST); - for (i = 0; i < 4; i++) { + for (i = 0; i < PCI_NUM_PINS; i++) { sysbus_init_irq(sbd, &s->irq[i]); } @@ -422,7 +422,7 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp) mapfn = pci_vpb_map_irq; } - pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4); + pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, PCI_NUM_PINS); /* Our memory regions are: * 0 : our control registers