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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id i11sm16786068wre.32.2020.10.10.10.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2020 10:26:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 16/20] hw/mips/cps: Expose input clock and connect it to CPU cores Date: Sat, 10 Oct 2020 19:26:13 +0200 Message-Id: <20201010172617.3079633-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201010172617.3079633-1-f4bug@amsat.org> References: <20201010172617.3079633-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Huacai Chen , Aleksandar Rikalo , Luc Michel , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Paolo Bonzini , Huacai Chen , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Expose a qdev input clock named 'clk', and connect it to each core. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/cps.h | 2 ++ hw/mips/cps.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 9e35a881366..859a8d4a674 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -21,6 +21,7 @@ #define MIPS_CPS_H #include "hw/sysbus.h" +#include "hw/clock.h" #include "hw/misc/mips_cmgcr.h" #include "hw/intc/mips_gic.h" #include "hw/misc/mips_cpc.h" @@ -43,6 +44,7 @@ struct MIPSCPSState { MIPSGICState gic; MIPSCPCState cpc; MIPSITUState itu; + Clock *clock; }; qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 23c0f87e41a..c332609f7b3 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -22,6 +22,7 @@ #include "qemu/module.h" #include "hw/mips/cps.h" #include "hw/mips/mips.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "hw/mips/cpudevs.h" #include "sysemu/kvm.h" @@ -38,6 +39,7 @@ static void mips_cps_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); MIPSCPSState *s = MIPS_CPS(obj); + s->clock = qdev_init_clock_in(DEVICE(obj), "clk", NULL, NULL); /* * Cover entire address space as there do not seem to be any * constraints for the base address of CPC and GIC. @@ -80,6 +82,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) errp)) { return; } + qdev_connect_clock_in(DEVICE(cpu), "clk", s->clock); if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { return;