diff mbox series

[V2,06/14] mips/: fix some comment spelling errors

Message ID 20201009064449.2336-7-zhaolichang@huawei.com
State New
Headers show
Series fix some comment spelling errors | expand

Commit Message

Lichang Zhao Oct. 9, 2020, 6:44 a.m. UTC 
I found that there are many spelling errors in the comments of qemu/target/mips.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
Reviewed-by: Philippe Mathieu-Daude<f4bug@amsat.org>
---
 target/mips/internal.h           |  2 +-
 target/mips/translate.c          | 10 +++++-----
 target/mips/translate_init.c.inc |  2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

Comments

Philippe Mathieu-Daudé Oct. 9, 2020, 2:36 p.m. UTC | #1 
On 10/9/20 8:44 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/mips.

> I used spellcheck to check the spelling errors and found some errors in the folder.

> 

> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

> Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> Reviewed-by: Philippe Mathieu-Daude<f4bug@amsat.org>


The line I sent is:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


> ---

>   target/mips/internal.h           |  2 +-

>   target/mips/translate.c          | 10 +++++-----

>   target/mips/translate_init.c.inc |  2 +-

>   3 files changed, 7 insertions(+), 7 deletions(-)
Philippe Mathieu-Daudé Oct. 9, 2020, 3:15 p.m. UTC | #2 
On 10/9/20 4:36 PM, Philippe Mathieu-Daudé wrote:
> On 10/9/20 8:44 AM, zhaolichang wrote:

>> I found that there are many spelling errors in the comments of 

>> qemu/target/mips.

>> I used spellcheck to check the spelling errors and found some errors 

>> in the folder.

>>

>> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

>> Reviewed-by: David Edmondson <david.edmondson@oracle.com>

>> Reviewed-by: Philippe Mathieu-Daude<f4bug@amsat.org>

> 

> The line I sent is:

> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


I'm queuing this patch on mips-next and will fix that along.

> 

>> ---

>>   target/mips/internal.h           |  2 +-

>>   target/mips/translate.c          | 10 +++++-----

>>   target/mips/translate_init.c.inc |  2 +-

>>   3 files changed, 7 insertions(+), 7 deletions(-)

>
diff mbox series

Patch

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9230..b811f547f3 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -188,7 +188,7 @@  static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
         /*
          * A MIPS configured with a vectorizing external interrupt controller
          * will feed a vector into the Cause pending lines. The core treats
-         * the status lines as a vector level, not as indiviual masks.
+         * the status lines as a vector level, not as individual masks.
          */
         r = pending > status;
     } else {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf7289..b4d009078e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3718,7 +3718,7 @@  static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
 
     t0 = tcg_temp_new();
     addr = tcg_temp_new();
-    /* compare the address against that of the preceeding LL */
+    /* compare the address against that of the preceding LL */
     gen_base_offset_addr(ctx, addr, base, offset);
     tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
     tcg_temp_free(addr);
@@ -25597,7 +25597,7 @@  static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
         }
         /* return resulting half-words to its original position */
         tcg_gen_shri_i32(t0, t0, 16);
-        /* finaly update the destination */
+        /* finally update the destination */
         tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
 
         tcg_temp_free(t1);
@@ -25633,7 +25633,7 @@  static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
         }
         /* return resulting half-words to its original position */
         tcg_gen_shri_i32(t0, t0, 16);
-        /* finaly update the destination */
+        /* finally update the destination */
         tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
 
         tcg_temp_free(t1);
@@ -25702,7 +25702,7 @@  static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
             }
             /* return resulting byte to its original position */
             tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
-            /* finaly update the destination */
+            /* finally update the destination */
             tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
         }
 
@@ -25742,7 +25742,7 @@  static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
             }
             /* return resulting byte to its original position */
             tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
-            /* finaly update the destination */
+            /* finally update the destination */
             tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
         }
 
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 637caccd89..c735b2bf66 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -995,7 +995,7 @@  static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
 
     /* MVPConf1 implemented, TLB sharable, no gating storage support,
        programmable cache partitioning implemented, number of allocatable
-       and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
+       and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
        implemented, 5 TCs implemented. */
     env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |