From patchwork Fri Oct 9 06:44:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lichang Zhao X-Patchwork-Id: 303361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B292EC433E7 for ; Fri, 9 Oct 2020 06:57:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A41C22245 for ; Fri, 9 Oct 2020 06:57:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A41C22245 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:47022 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmL7-000220-VB for qemu-devel@archiver.kernel.org; Fri, 09 Oct 2020 02:57:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAG-0005xw-9f; Fri, 09 Oct 2020 02:46:04 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:55030 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAE-0001J8-5C; Fri, 09 Oct 2020 02:46:03 -0400 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 28578F2F243A03987B3E; Fri, 9 Oct 2020 14:45:58 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:51 +0800 From: zhaolichang To: Subject: [PATCH V2 03/14] riscv/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:38 +0800 Message-ID: <20201009064449.2336-4-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:58 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" I found that there are many spelling errors in the comments of qemu/target/riscv. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 2 +- target/riscv/csr.c | 6 +++--- target/riscv/vector_helper.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..f40a0b26a3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } } else { - qemu_log("vector verison is not specified, " + qemu_log("vector version is not specified, " "use the default value v0.7.1\n"); } set_vext_version(env, vext_version); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..6e1155560b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -536,7 +536,7 @@ /* Leaf page shift amount */ #define PGSHIFT 12 -/* Default Reset Vector adress */ +/* Default Reset Vector address */ #define DEFAULT_RSTVEC 0x1000 /* Exception causes */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..93e117020d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) return 0; } -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) { if (env->priv_ver < PRIV_VERSION_1_11_0) { @@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) return 0; } -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) { if (env->priv_ver < PRIV_VERSION_1_11_0) { @@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, !riscv_cpu_virt_enabled(env)) { /* * We are in S mode without virtualisation, therefore we are in HS Mode. - * Add 1 to the effective privledge level to allow us to access the + * Add 1 to the effective privilege level to allow us to access the * Hypervisor CSRs. */ effective_priv++; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a156573d28..fa89a6e6c1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr, uint32_t wd, uint32_t idx, CPURISCVState *env, uintptr_t retaddr); -/* no atomic opreation for vector atomic insructions */ +/* no atomic operation for vector atomic insructions */ #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) #define DO_XOR(N, M) (N ^ M)