| Message ID | 20201009064449.2336-4-zhaolichang@huawei.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | fix some comment spelling errors | expand |
Hi, On Fri, Oct 9, 2020 at 2:55 PM zhaolichang <zhaolichang@huawei.com> wrote: > > I found that there are many spelling errors in the comments of qemu/target/riscv. > I used spellcheck to check the spelling errors and found some errors in the folder. > > Signed-off-by: zhaolichang <zhaolichang@huawei.com> > Reviewed-by: David Edmondson <david.edmondson@oracle.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 2 +- > target/riscv/cpu_bits.h | 2 +- > target/riscv/csr.c | 6 +++--- > target/riscv/vector_helper.c | 2 +- > 4 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0bbfd7f457..f40a0b26a3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > } else { > - qemu_log("vector verison is not specified, " > + qemu_log("vector version is not specified, " > "use the default value v0.7.1\n"); > } > set_vext_version(env, vext_version); > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index bd36062877..6e1155560b 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -536,7 +536,7 @@ > /* Leaf page shift amount */ > #define PGSHIFT 12 > > -/* Default Reset Vector adress */ > +/* Default Reset Vector address */ > #define DEFAULT_RSTVEC 0x1000 > > /* Exception causes */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index aaef6c6f20..93e117020d 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) > return 0; > } > > -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) > { > if (env->priv_ver < PRIV_VERSION_1_11_0) { > @@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) > return 0; > } > > -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) > { > if (env->priv_ver < PRIV_VERSION_1_11_0) { > @@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, > !riscv_cpu_virt_enabled(env)) { > /* > * We are in S mode without virtualisation, therefore we are in HS Mode. > - * Add 1 to the effective privledge level to allow us to access the > + * Add 1 to the effective privilege level to allow us to access the > * Hypervisor CSRs. > */ > effective_priv++; > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index a156573d28..fa89a6e6c1 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr, > uint32_t wd, uint32_t idx, CPURISCVState *env, > uintptr_t retaddr); > > -/* no atomic opreation for vector atomic insructions */ > +/* no atomic operation for vector atomic insructions */ There is still one typo here: instructions > #define DO_SWAP(N, M) (M) > #define DO_AND(N, M) (N & M) > #define DO_XOR(N, M) (N ^ M) > -- Regards, Bin
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..f40a0b26a3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } } else { - qemu_log("vector verison is not specified, " + qemu_log("vector version is not specified, " "use the default value v0.7.1\n"); } set_vext_version(env, vext_version); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..6e1155560b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -536,7 +536,7 @@ /* Leaf page shift amount */ #define PGSHIFT 12 -/* Default Reset Vector adress */ +/* Default Reset Vector address */ #define DEFAULT_RSTVEC 0x1000 /* Exception causes */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..93e117020d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) return 0; } -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) { if (env->priv_ver < PRIV_VERSION_1_11_0) { @@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) return 0; } -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) { if (env->priv_ver < PRIV_VERSION_1_11_0) { @@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, !riscv_cpu_virt_enabled(env)) { /* * We are in S mode without virtualisation, therefore we are in HS Mode. - * Add 1 to the effective privledge level to allow us to access the + * Add 1 to the effective privilege level to allow us to access the * Hypervisor CSRs. */ effective_priv++; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a156573d28..fa89a6e6c1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr, uint32_t wd, uint32_t idx, CPURISCVState *env, uintptr_t retaddr); -/* no atomic opreation for vector atomic insructions */ +/* no atomic operation for vector atomic insructions */ #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) #define DO_XOR(N, M) (N ^ M)