From patchwork Fri Oct 9 06:44:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lichang Zhao X-Patchwork-Id: 303353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5572DC433E7 for ; Fri, 9 Oct 2020 07:07:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CDE4322260 for ; Fri, 9 Oct 2020 07:07:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CDE4322260 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmUu-0006Xn-U3 for qemu-devel@archiver.kernel.org; Fri, 09 Oct 2020 03:07:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAf-0006B6-05; Fri, 09 Oct 2020 02:46:29 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5213 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-0001KR-Jy; Fri, 09 Oct 2020 02:46:28 -0400 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 3BAF7A5FC36138034763; Fri, 9 Oct 2020 14:46:13 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:46:04 +0800 From: zhaolichang To: Subject: [PATCH V2 14/14] target/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:49 +0800 Message-ID: <20201009064449.2336-15-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:42 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" I found that there are many spelling errors in the comments of qemu/target. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude --- target/openrisc/cpu.h | 2 +- target/sparc/asi.h | 2 +- target/unicore32/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bd42faf144..8ca8605301 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState { int is_counting; uint32_t picmr; /* Interrupt mask register */ - uint32_t picsr; /* Interrupt contrl register*/ + uint32_t picsr; /* Interrupt control register*/ #endif void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; diff --git a/target/sparc/asi.h b/target/sparc/asi.h index bb58735ddb..4e9f1d59ed 100644 --- a/target/sparc/asi.h +++ b/target/sparc/asi.h @@ -231,7 +231,7 @@ #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index d4b06df672..2e91b05c15 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg) { if (reg == 31) { uint32_t addr; - /* normaly, since we updated PC */ + /* normally, since we updated PC */ addr = (long)s->pc; tcg_gen_movi_i32(var, addr); } else {