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Tue, 29 Sep 2020 19:19:37 -0400 (EDT) From: Klaus Jensen To: qemu-devel@nongnu.org Subject: [PATCH v2 14/14] hw/block/nvme: allow open to close transitions by controller Date: Wed, 30 Sep 2020 01:19:17 +0200 Message-Id: <20200929231917.433586-15-its@irrelevant.dk> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929231917.433586-1-its@irrelevant.dk> References: <20200929231917.433586-1-its@irrelevant.dk> MIME-Version: 1.0 Received-SPF: pass client-ip=64.147.123.27; envelope-from=its@irrelevant.dk; helo=wnew2-smtp.messagingengine.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/29 17:46:07 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Klaus Jensen Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Allow the controller to release open resources by transitioning implicitly and explicitly opened zones to closed. This is done using a naive "least recently opened" strategy. Signed-off-by: Klaus Jensen --- hw/block/nvme-ns.h | 5 ++ hw/block/nvme-ns.c | 5 ++ hw/block/nvme.c | 105 +++++++++++++++++++++++++++++++++++------- hw/block/trace-events | 5 ++ 4 files changed, 103 insertions(+), 17 deletions(-) diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h index ff34cd37af7d..491a77f3ae2f 100644 --- a/hw/block/nvme-ns.h +++ b/hw/block/nvme-ns.h @@ -62,6 +62,8 @@ typedef struct NvmeZone { uint8_t *zde; uint64_t wp_staging; + + QTAILQ_ENTRY(NvmeZone) lru_entry; } NvmeZone; typedef struct NvmeNamespace { @@ -101,6 +103,9 @@ typedef struct NvmeNamespace { struct { uint32_t open; uint32_t active; + + QTAILQ_HEAD(, NvmeZone) lru_open; + QTAILQ_HEAD(, NvmeZone) lru_active; } resources; } zns; } NvmeNamespace; diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index 9584fbb3f62d..26c9f846417a 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -225,6 +225,9 @@ void nvme_ns_zns_init_zone_state(NvmeNamespace *ns) ns->zns.resources.open = ns->params.zns.mor != 0xffffffff ? ns->params.zns.mor + 1 : ns->zns.num_zones; + QTAILQ_INIT(&ns->zns.resources.lru_open); + QTAILQ_INIT(&ns->zns.resources.lru_active); + for (int i = 0; i < ns->zns.num_zones; i++) { NvmeZone *zone = &ns->zns.zones[i]; zone->zd = &ns->zns.zd[i]; @@ -248,6 +251,8 @@ void nvme_ns_zns_init_zone_state(NvmeNamespace *ns) if (ns->zns.resources.active) { ns->zns.resources.active--; + QTAILQ_INSERT_TAIL(&ns->zns.resources.lru_active, zone, + lru_entry); continue; } diff --git a/hw/block/nvme.c b/hw/block/nvme.c index fc5b119e3f35..34093f33ad1a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1209,12 +1209,61 @@ static inline void nvme_zone_reset_wp(NvmeZone *zone) zone->wp_staging = nvme_zslba(zone); } -static uint16_t nvme_zrm_transition(NvmeNamespace *ns, NvmeZone *zone, - NvmeZoneState to) +static uint16_t nvme_zrm_transition(NvmeCtrl *n, NvmeNamespace *ns, + NvmeZone *zone, NvmeZoneState to, + NvmeRequest *req); + +static uint16_t nvme_zrm_release_open(NvmeCtrl *n, NvmeNamespace *ns, + NvmeRequest *req) +{ + NvmeZone *candidate; + NvmeZoneState zs; + uint16_t status; + + trace_pci_nvme_zone_zrm_release_open(nvme_cid(req), ns->params.nsid); + + QTAILQ_FOREACH(candidate, &ns->zns.resources.lru_open, lru_entry) { + zs = nvme_zs(candidate); + + trace_pci_nvme_zone_zrm_candidate(nvme_cid(req), ns->params.nsid, + nvme_zslba(candidate), + nvme_wp(candidate), zs); + + /* skip explicitly opened zones */ + if (zs == NVME_ZS_ZSEO) { + continue; + } + + /* the zone cannot be closed if it is currently writing */ + if (candidate->wp_staging != nvme_wp(candidate)) { + continue; + } + + status = nvme_zrm_transition(n, ns, candidate, NVME_ZS_ZSC, req); + if (status) { + return status; + } + + if (nvme_zns_commit_zone(ns, candidate) < 0) { + return NVME_INTERNAL_DEV_ERROR; + } + + return NVME_SUCCESS; + } + + return NVME_TOO_MANY_OPEN_ZONES; +} + +static uint16_t nvme_zrm_transition(NvmeCtrl *n, NvmeNamespace *ns, + NvmeZone *zone, NvmeZoneState to, + NvmeRequest *req) { NvmeZoneState from = nvme_zs(zone); + uint16_t status; + + trace_pci_nvme_zone_zrm_transition(nvme_cid(req), ns->params.nsid, + nvme_zslba(zone), nvme_zs(zone), to); - /* fast path */ if (from == to) { return NVME_SUCCESS; } @@ -1229,25 +1278,32 @@ static uint16_t nvme_zrm_transition(NvmeNamespace *ns, NvmeZone *zone, case NVME_ZS_ZSC: if (!ns->zns.resources.active) { + trace_pci_nvme_err_too_many_active_zones(nvme_cid(req)); return NVME_TOO_MANY_ACTIVE_ZONES; } ns->zns.resources.active--; + QTAILQ_INSERT_TAIL(&ns->zns.resources.lru_active, zone, lru_entry); break; case NVME_ZS_ZSIO: case NVME_ZS_ZSEO: if (!ns->zns.resources.active) { + trace_pci_nvme_err_too_many_active_zones(nvme_cid(req)); return NVME_TOO_MANY_ACTIVE_ZONES; } if (!ns->zns.resources.open) { - return NVME_TOO_MANY_OPEN_ZONES; + status = nvme_zrm_release_open(n, ns, req); + if (status) { + return status; + } } ns->zns.resources.active--; ns->zns.resources.open--; + QTAILQ_INSERT_TAIL(&ns->zns.resources.lru_open, zone, lru_entry); break; @@ -1276,11 +1332,15 @@ static uint16_t nvme_zrm_transition(NvmeNamespace *ns, NvmeZone *zone, case NVME_ZS_ZSF: case NVME_ZS_ZSRO: ns->zns.resources.active++; + ns->zns.resources.open++; + QTAILQ_REMOVE(&ns->zns.resources.lru_open, zone, lru_entry); - /* fallthrough */ + break; case NVME_ZS_ZSC: ns->zns.resources.open++; + QTAILQ_REMOVE(&ns->zns.resources.lru_open, zone, lru_entry); + QTAILQ_INSERT_TAIL(&ns->zns.resources.lru_active, zone, lru_entry); break; @@ -1305,16 +1365,22 @@ static uint16_t nvme_zrm_transition(NvmeNamespace *ns, NvmeZone *zone, case NVME_ZS_ZSF: case NVME_ZS_ZSRO: ns->zns.resources.active++; + QTAILQ_REMOVE(&ns->zns.resources.lru_active, zone, lru_entry); break; case NVME_ZS_ZSIO: case NVME_ZS_ZSEO: if (!ns->zns.resources.open) { - return NVME_TOO_MANY_OPEN_ZONES; + status = nvme_zrm_release_open(n, ns, req); + if (status) { + return status; + } } ns->zns.resources.open--; + QTAILQ_REMOVE(&ns->zns.resources.lru_active, zone, lru_entry); + QTAILQ_INSERT_TAIL(&ns->zns.resources.lru_open, zone, lru_entry); break; @@ -1338,6 +1404,9 @@ static uint16_t nvme_zrm_transition(NvmeNamespace *ns, NvmeZone *zone, case NVME_ZS_ZSF: switch (to) { + case NVME_ZS_ZSF: + return NVME_SUCCESS; + case NVME_ZS_ZSE: nvme_zone_reset_wp(zone); @@ -1376,7 +1445,9 @@ static void nvme_zns_advance_wp(NvmeRequest *req) wp += nlb; zone->zd->wp = cpu_to_le64(wp); if (wp == nvme_zslba(zone) + nvme_zcap(zone)) { - nvme_zrm_transition(req->ns, zone, NVME_ZS_ZSF); + NvmeCtrl *n = nvme_ctrl(req); + + nvme_zrm_transition(n, req->ns, zone, NVME_ZS_ZSF, req); if (nvme_zns_commit_zone(req->ns, zone) < 0) { req->status = NVME_INTERNAL_DEV_ERROR; } @@ -1433,6 +1504,7 @@ static void nvme_rw_cb(void *opaque, int ret) uint64_t slba = le64_to_cpu(rw->slba); NvmeZone *zone = nvme_ns_get_zone(ns, slba); + NvmeCtrl *n = nvme_ctrl(req); /* * Transition the zone to read-only on write fault and offline @@ -1441,7 +1513,7 @@ static void nvme_rw_cb(void *opaque, int ret) NvmeZoneState zs = status == NVME_WRITE_FAULT ? NVME_ZS_ZSRO : NVME_ZS_ZSO; - nvme_zrm_transition(ns, zone, zs); + nvme_zrm_transition(n, ns, zone, zs, req); if (nvme_zns_commit_zone(ns, zone) < 0) { req->status = NVME_INTERNAL_DEV_ERROR; } @@ -1535,7 +1607,7 @@ static uint16_t nvme_zone_mgmt_send_close(NvmeCtrl *n, NvmeRequest *req, break; } - status = nvme_zrm_transition(ns, zone, NVME_ZS_ZSC); + status = nvme_zrm_transition(n, ns, zone, NVME_ZS_ZSC, req); if (status) { return status; } @@ -1560,7 +1632,7 @@ static uint16_t nvme_zone_mgmt_send_finish(NvmeCtrl *n, NvmeRequest *req, return NVME_SUCCESS; } - status = nvme_zrm_transition(ns, zone, NVME_ZS_ZSF); + status = nvme_zrm_transition(n, ns, zone, NVME_ZS_ZSF, req); if (status) { return status; } @@ -1585,7 +1657,7 @@ static uint16_t nvme_zone_mgmt_send_open(NvmeCtrl *n, NvmeRequest *req, return NVME_SUCCESS; } - status = nvme_zrm_transition(ns, zone, NVME_ZS_ZSEO); + status = nvme_zrm_transition(n, ns, zone, NVME_ZS_ZSEO, req); if (status) { return status; } @@ -1621,7 +1693,7 @@ static uint16_t nvme_zone_mgmt_send_reset(NvmeCtrl *n, NvmeRequest *req, return NVME_INTERNAL_DEV_ERROR; } - nvme_zrm_transition(ns, zone, NVME_ZS_ZSE); + nvme_zrm_transition(n, ns, zone, NVME_ZS_ZSE, req); if (nvme_zns_commit_zone(ns, zone) < 0) { return NVME_INTERNAL_DEV_ERROR; } @@ -1652,7 +1724,7 @@ static uint16_t nvme_zone_mgmt_send_offline(NvmeCtrl *n, NvmeRequest *req, return NVME_INTERNAL_DEV_ERROR; } - nvme_zrm_transition(ns, zone, NVME_ZS_ZSO); + nvme_zrm_transition(n, ns, zone, NVME_ZS_ZSO, req); if (nvme_zns_commit_zone(ns, zone) < 0) { return NVME_INTERNAL_DEV_ERROR; } @@ -1696,7 +1768,7 @@ static uint16_t nvme_zone_mgmt_send_set_zde(NvmeCtrl *n, NvmeRequest *req, return status; } - status = nvme_zrm_transition(ns, zone, NVME_ZS_ZSC); + status = nvme_zrm_transition(n, ns, zone, NVME_ZS_ZSC, req); if (status) { return status; } @@ -2122,7 +2194,7 @@ static uint16_t nvme_rwz(NvmeCtrl *n, NvmeRequest *req) case NVME_ZS_ZSEO: break; default: - status = nvme_zrm_transition(ns, zone, NVME_ZS_ZSIO); + status = nvme_zrm_transition(n, ns, zone, NVME_ZS_ZSIO, req); if (status) { goto invalid; } @@ -3348,11 +3420,10 @@ static void nvme_clear_ctrl(NvmeCtrl *n) if (nvme_ns_zoned(ns)) { for (int i = 0; i < ns->zns.num_zones; i++) { NvmeZone *zone = &ns->zns.zones[i]; - switch (nvme_zs(zone)) { case NVME_ZS_ZSIO: case NVME_ZS_ZSEO: - nvme_zrm_transition(ns, zone, NVME_ZS_ZSC); + nvme_zrm_transition(n, ns, zone, NVME_ZS_ZSC, NULL); nvme_zns_commit_zone(ns, zone); break; default: diff --git a/hw/block/trace-events b/hw/block/trace-events index 929409b79b41..18f7b24ef5e9 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -88,6 +88,9 @@ pci_nvme_mmio_read(uint64_t addr) "addr 0x%"PRIx64"" pci_nvme_mmio_write(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64"" pci_nvme_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16"" pci_nvme_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tail) "sqid %"PRIu16" new_tail %"PRIu16"" +pci_nvme_zone_zrm_transition(uint16_t cid, uint32_t nsid, uint64_t zslba, uint8_t from, uint8_t to) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" from 0x%"PRIx8" to 0x%"PRIx8"" +pci_nvme_zone_zrm_candidate(uint16_t cid, uint32_t nsid, uint64_t zslba, uint64_t wp, uint8_t zc) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" wp 0x%"PRIx64" zc 0x%"PRIx8"" +pci_nvme_zone_zrm_release_open(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu32"" pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask set, data=0x%"PRIx64", new_mask=0x%"PRIx64"" pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask clr, data=0x%"PRIx64", new_mask=0x%"PRIx64"" pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=0x%"PRIx64"" @@ -115,6 +118,8 @@ pci_nvme_err_zone_is_read_only(uint16_t cid, uint64_t slba) "cid %"PRIu16" lba 0 pci_nvme_err_zone_invalid_write(uint16_t cid, uint64_t slba, uint64_t wp) "cid %"PRIu16" lba 0x%"PRIx64" wp 0x%"PRIx64"" pci_nvme_err_zone_boundary(uint16_t cid, uint64_t slba, uint32_t nlb, uint64_t zcap) "cid %"PRIu16" lba 0x%"PRIx64" nlb %"PRIu32" zcap 0x%"PRIx64"" pci_nvme_err_zone_pending_writes(uint16_t cid, uint64_t zslba, uint64_t wp, uint64_t wp_staging) "cid %"PRIu16" zslba 0x%"PRIx64" wp 0x%"PRIx64" wp_staging 0x%"PRIx64"" +pci_nvme_err_too_many_active_zones(uint16_t cid) "cid %"PRIu16"" +pci_nvme_err_too_many_open_zones(uint16_t cid) "cid %"PRIu16"" pci_nvme_err_invalid_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0x%"PRIx8"" pci_nvme_err_invalid_num_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0x%"PRIx8"" pci_nvme_err_invalid_sgl_excess_length(uint16_t cid) "cid %"PRIu16""