diff mbox series

[PULL,30/57] i386/cpu: Clear FEAT_XSAVE_COMP_{LO, HI} when XSAVE is not available

Message ID 20200919155916.1046398-31-pbonzini@redhat.com
State New
Headers show
Series Misc patches for 2020-09-19 | expand

Commit Message

Paolo Bonzini Sept. 19, 2020, 3:58 p.m. UTC 
From: Xiaoyao Li <xiaoyao.li@intel.com>

Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the
processor provides no further enumeration through CPUID function 0DH.
QEMU does not do this for "-cpu host,-xsave".

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20200716082019.215316-2-xiaoyao.li@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7603784351..053385c2b4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6372,6 +6372,8 @@  static void x86_cpu_enable_xsave_components(X86CPU *cpu)
     uint64_t mask;
 
     if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
+        env->features[FEAT_XSAVE_COMP_LO] = 0;
+        env->features[FEAT_XSAVE_COMP_HI] = 0;
         return;
     }