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[83.57.170.65]) by smtp.gmail.com with ESMTPSA id t188sm9598698wmf.41.2020.09.12.01.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Sep 2020 01:29:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 1/2] hw/mips/mipssim: Use MMIO serial device on fake ISA I/O Date: Sat, 12 Sep 2020 10:29:43 +0200 Message-Id: <20200912082944.890972-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200912082944.890972-1-f4bug@amsat.org> References: <20200912082944.890972-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Aleksandar Rikalo , "Michael S. Tsirkin" , Richard Henderson , Jiaxun Yang , Aleksandar Markovic , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The 'mipssim' is not a real hardware, it is a simulator. There is an ISA MMIO space mapped at 0x1fd00000, however this is not a real ISA bus (no ISA IRQ). So can not use the TYPE_ISA_SERIAL device... Instead we have been using a plain MMIO device, but named it IO. TYPE_SERIAL_IO is a subset of TYPE_SERIAL_MM, using regshift=0 and endianness=DEVICE_LITTLE_ENDIAN. Directly use the TYPE_SERIAL_MM device, enforcing the regshift/endianness values. 'regshift' default is already '0'. 'endianness' is meaningless for 8-bit accesses. This change breaks migration back compatibility, but this is not an issue for the mipssim machine. Suggested-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/mipssim.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index 1b3b7622035..5d4ad74828d 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -216,10 +216,11 @@ mips_mipssim_init(MachineState *machine) * MIPS CPU INT2, which is interrupt 4. */ if (serial_hd(0)) { - DeviceState *dev = qdev_new(TYPE_SERIAL_IO); + DeviceState *dev = qdev_new(TYPE_SERIAL_MM); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); - qdev_set_legacy_instance_id(dev, 0x3f8, 2); + qdev_prop_set_uint8(dev, "regshift", 0); + qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]); sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8,