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[83.57.170.65]) by smtp.gmail.com with ESMTPSA id x2sm6783804wrl.13.2020.09.10.00.23.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 00:23:29 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 2/2] hw/ppc/ppc4xx_pci: Replace magic value by the PCI_NUM_PINS definition Date: Thu, 10 Sep 2020 09:23:25 +0200 Message-Id: <20200910072325.439344-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200910072325.439344-1-f4bug@amsat.org> References: <20200910072325.439344-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-trivial@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Replace the magic '4' value by the PCI_NUM_PINS definition. Suggested-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/ppc4xx_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c index 503ef46b39a..930be78361d 100644 --- a/hw/ppc/ppc4xx_pci.c +++ b/hw/ppc/ppc4xx_pci.c @@ -54,7 +54,7 @@ struct PPC4xxPCIState { struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS]; struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS]; - qemu_irq irq[4]; + qemu_irq irq[PCI_NUM_PINS]; MemoryRegion container; MemoryRegion iomem;