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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This wasn't actually used for anything, really. All variable operands must accept registers, and which are indicated by the set in TCGArgConstraint.regs. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - tcg/tcg.c | 15 ++++----------- tcg/aarch64/tcg-target.c.inc | 3 --- tcg/arm/tcg-target.c.inc | 3 --- tcg/i386/tcg-target.c.inc | 11 ----------- tcg/mips/tcg-target.c.inc | 3 --- tcg/ppc/tcg-target.c.inc | 5 ----- tcg/riscv/tcg-target.c.inc | 2 -- tcg/s390/tcg-target.c.inc | 4 ---- tcg/sparc/tcg-target.c.inc | 5 ----- tcg/tci/tcg-target.c.inc | 1 - 11 files changed, 4 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 63955ac85b..3168315bb8 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -979,7 +979,6 @@ void tcg_dump_op_count(void); #define TCG_CT_ALIAS 0x80 #define TCG_CT_IALIAS 0x40 #define TCG_CT_NEWREG 0x20 /* output requires a new register */ -#define TCG_CT_REG 0x01 #define TCG_CT_CONST 0x02 /* any constant of register size */ typedef struct TCGArgConstraint { diff --git a/tcg/tcg.c b/tcg/tcg.c index 0a04b6cbd9..a618497c94 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2194,21 +2194,14 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) /* we give more priority to constraints with less registers */ static int get_constraint_priority(const TCGOpDef *def, int k) { - const TCGArgConstraint *arg_ct; + const TCGArgConstraint *arg_ct = &def->args_ct[k]; + int n; - int i, n; - arg_ct = &def->args_ct[k]; if (arg_ct->ct & TCG_CT_ALIAS) { /* an alias is equivalent to a single register */ n = 1; } else { - if (!(arg_ct->ct & TCG_CT_REG)) - return 0; - n = 0; - for(i = 0; i < TCG_TARGET_NB_REGS; i++) { - if (tcg_regset_test_reg(arg_ct->regs, i)) - n++; - } + n = ctpop64(arg_ct->regs); } return TCG_TARGET_NB_REGS - n + 1; } @@ -2276,7 +2269,7 @@ static void process_op_defs(TCGContext *s) int oarg = *ct_str - '0'; tcg_debug_assert(ct_str == tdefs->args_ct_str[i]); tcg_debug_assert(oarg < def->nb_oargs); - tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG); + tcg_debug_assert(def->args_ct[oarg].regs != 0); /* TCG_CT_ALIAS is for the output arguments. The input is tagged with TCG_CT_IALIAS. */ def->args_ct[i] = def->args_ct[oarg]; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d4b7cb4867..479a9d26be 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -128,15 +128,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': /* general registers */ - ct->ct |= TCG_CT_REG; ct->regs |= 0xffffffffu; break; case 'w': /* advsimd registers */ - ct->ct |= TCG_CT_REG; ct->regs |= 0xffffffff00000000ull; break; case 'l': /* qemu_ld / qemu_st address, data_reg */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffffu; #ifdef CONFIG_SOFTMMU /* x0 and x1 will be overwritten when reading the tlb entry, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 978eb1dd70..62c37a954b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -253,13 +253,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; break; /* qemu_ld address */ case 'l': - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; #ifdef CONFIG_SOFTMMU /* r0-r2,lr will be overwritten when reading the tlb entry, @@ -274,7 +272,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, /* qemu_st address & data */ case 's': - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) and r0-r1 doing the byte swapping, so don't use these. */ diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 8661ec3393..2f696074ab 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -208,42 +208,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch(*ct_str++) { case 'a': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EAX); break; case 'b': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EBX); break; case 'c': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_ECX); break; case 'd': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EDX); break; case 'S': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_ESI); break; case 'D': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EDI); break; case 'q': /* A register that can be used as a byte operand. */ - ct->ct |= TCG_CT_REG; ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; break; case 'Q': /* A register with an addressable second byte (e.g. %ah). */ - ct->ct |= TCG_CT_REG; ct->regs = 0xf; break; case 'r': /* A general register. */ - ct->ct |= TCG_CT_REG; ct->regs |= ALL_GENERAL_REGS; break; case 'W': @@ -252,13 +243,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'x': /* A vector register. */ - ct->ct |= TCG_CT_REG; ct->regs |= ALL_VECTOR_REGS; break; /* qemu_ld/st address constraint */ case 'L': - ct->ct |= TCG_CT_REG; ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; tcg_regset_reset_reg(ct->regs, TCG_REG_L0); tcg_regset_reset_reg(ct->regs, TCG_REG_L1); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d49a02bb03..98c6a41caf 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -195,11 +195,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch(*ct_str++) { case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'L': /* qemu_ld input arg constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; tcg_regset_reset_reg(ct->regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) @@ -209,7 +207,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, #endif break; case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; tcg_regset_reset_reg(ct->regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 450b555522..7a5760bb23 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -224,19 +224,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'A': case 'B': case 'C': case 'D': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A'); break; case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'v': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff00000000ull; break; case 'L': /* qemu_ld constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU @@ -245,7 +241,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, #endif break; case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 0a69839adb..d536f3ccc1 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -137,12 +137,10 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'L': /* qemu_ld/qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ #if defined(CONFIG_SOFTMMU) diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 9cd266a2d0..c5e096449b 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -408,23 +408,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': /* all registers */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; break; case 'L': /* qemu_ld/st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffff; tcg_regset_reset_reg(ct->regs, TCG_REG_R2); tcg_regset_reset_reg(ct->regs, TCG_REG_R3); tcg_regset_reset_reg(ct->regs, TCG_REG_R4); break; case 'a': /* force R2 for division */ - ct->ct |= TCG_CT_REG; ct->regs = 0; tcg_regset_set_reg(ct->regs, TCG_REG_R2); break; case 'b': /* force R3 for division */ - ct->ct |= TCG_CT_REG; ct->regs = 0; tcg_regset_set_reg(ct->regs, TCG_REG_R3); break; diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index c662293fc7..44373d742b 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -325,15 +325,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'R': - ct->ct |= TCG_CT_REG; ct->regs = ALL_64; break; case 'A': /* qemu_ld/st address constraint */ - ct->ct |= TCG_CT_REG; ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; reserve_helpers: tcg_regset_reset_reg(ct->regs, TCG_REG_O0); @@ -341,11 +338,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, tcg_regset_reset_reg(ct->regs, TCG_REG_O2); break; case 's': /* qemu_st data 32-bit constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; goto reserve_helpers; case 'S': /* qemu_st data 64-bit constraint */ - ct->ct |= TCG_CT_REG; ct->regs = ALL_64; goto reserve_helpers; case 'I': diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index a7215f346f..231b9b1775 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -392,7 +392,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'r': case 'L': /* qemu_ld constraint */ case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; ct->regs = BIT(TCG_TARGET_NB_REGS) - 1; break; default: