[02/43] tcg: Drop union from TCGArgConstraint

Message ID	20200909001647.532249-3-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 02/43] tcg: Drop union from TCGArgConstraint Date: Tue, 8 Sep 2020 17:16:06 -0700 Message-Id: <20200909001647.532249-3-richard.henderson@linaro.org> In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org> References: <20200909001647.532249-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg patch queue \| expand [00/43] tcg patch queue [01/43] tcg: Adjust simd_desc size encoding [02/43] tcg: Drop union from TCGArgConstraint [03/43] tcg: Move sorted_args into TCGArgConstraint.sort_index [04/43] tcg: Remove TCG_CT_REG [05/43] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields [06/43] tcg: Remove TCGOpDef.used [07/43] tcg/i386: Fix dupi for avx2 32-bit hosts [08/43] tcg: Fix generation of dupi_vec for 32-bit host [09/43] tcg/optimize: Fold dup2_vec [10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec [11/43] tcg: Use tcg_out_dupi_vec from temp_load [12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t [13/43] tcg: Consolidate 3 bits into enum TCGTempKind [14/43] tcg: Add temp_readonly [15/43] tcg: Expand TCGTemp.val to 64-bits [16/43] tcg: Rename struct tcg_temp_info to TempOptInfo [17/43] tcg: Expand TempOptInfo to 64-bits [18/43] tcg: Introduce TYPE_CONST temporaries [19/43] tcg/optimize: Improve find_better_copy [20/43] tcg/optimize: Adjust TempOptInfo allocation [21/43] tcg/optimize: Use tcg_constant_internal with constant folding [22/43] tcg: Convert tcg_gen_dupi_vec to TCG_CONST [23/43] tcg: Use tcg_constant_i32 with icount expander [24/43] tcg: Use tcg_constant_{i32,i64} with tcg int expanders [25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins [26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders [27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes [28/43] tcg: Remove movi and dupi opcodes [29/43] tcg: Add tcg_reg_alloc_dup2 [30/43] tcg/i386: Use tcg_constant_vec with tcg vec expanders [31/43] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec [32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders [33/43] tcg/aarch64: Use tcg_constant_vec with tcg vec expanders [34/43] tcg: Add tcg-constr.c.inc [35/43] tcg/i386: Convert to tcg-constr.c.inc [36/43] tcg/aarch64: Convert to tcg-constr.c.inc [37/43] tcg/arm: Convert to tcg-constr.c.inc [38/43] tcg/mips: Convert to tcg-constr.c.inc [39/43] tcg/ppc: Convert to tcg-constr.c.inc [40/43] tcg/riscv: Convert to tcg-constr.c.inc [41/43] tcg/s390: Convert to tcg-constr.c.inc [42/43] tcg/sparc: Convert to tcg-constr.c.inc [43/43] tcg/tci: Convert to tcg-constr.c.inc

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 53ce94c2c5..a5a0ea4ada 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -985,9 +985,7 @@ void tcg_dump_op_count(void); typedef struct TCGArgConstraint { uint16_t ct; uint8_t alias_index; - union { - TCGRegSet regs; - } u; + TCGRegSet regs; } TCGArgConstraint; #define TCG_MAX_OP_ARGS 16 diff --git a/tcg/tcg.c b/tcg/tcg.c index 62f299e36e..dcb38bf1e0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2210,7 +2210,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k) return 0; n = 0; for(i = 0; i < TCG_TARGET_NB_REGS; i++) { - if (tcg_regset_test_reg(arg_ct->u.regs, i)) + if (tcg_regset_test_reg(arg_ct->regs, i)) n++; } } @@ -2268,7 +2268,7 @@ static void process_op_defs(TCGContext *s) /* Incomplete TCGTargetOpDef entry. */ tcg_debug_assert(ct_str != NULL); - def->args_ct[i].u.regs = 0; + def->args_ct[i].regs = 0; def->args_ct[i].ct = 0; while (*ct_str != '\0') { switch(*ct_str) { @@ -2855,13 +2855,13 @@ static void liveness_pass_1(TCGContext *s) pset = la_temp_pref(ts); set = *pset; - set &= ct->u.regs; + set &= ct->regs; if (ct->ct & TCG_CT_IALIAS) { set &= op->output_pref[ct->alias_index]; } /* If the combination is not possible, restart. */ if (set == 0) { - set = ct->u.regs; + set = ct->regs; } *pset = set; } @@ -3551,8 +3551,8 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) return; } - dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs; - dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs; + dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; + dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs; /* Allocate the output register now. */ if (ots->val_type != TEMP_VAL_REG) { @@ -3706,10 +3706,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } } - temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs); + temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs); reg = ts->reg; - if (tcg_regset_test_reg(arg_ct->u.regs, reg)) { + if (tcg_regset_test_reg(arg_ct->regs, reg)) { /* nothing to do : the constraint is satisfied */ } else { allocate_in_reg: @@ -3717,7 +3717,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) and move the temporary register into it */ temp_load(s, ts, tcg_target_available_regs[ts->type], i_allocated_regs, 0); - reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, + reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { /* @@ -3772,11 +3772,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) && !const_args[arg_ct->alias_index]) { reg = new_args[arg_ct->alias_index]; } else if (arg_ct->ct & TCG_CT_NEWREG) { - reg = tcg_reg_alloc(s, arg_ct->u.regs, + reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs | o_allocated_regs, op->output_pref[k], ts->indirect_base); } else { - reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, + reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, op->output_pref[k], ts->indirect_base); } tcg_regset_set_reg(o_allocated_regs, reg); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 948c35d825..d4b7cb4867 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -129,22 +129,22 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': /* general registers */ ct->ct |= TCG_CT_REG; - ct->u.regs |= 0xffffffffu; + ct->regs |= 0xffffffffu; break; case 'w': /* advsimd registers */ ct->ct |= TCG_CT_REG; - ct->u.regs |= 0xffffffff00000000ull; + ct->regs |= 0xffffffff00000000ull; break; case 'l': /* qemu_ld / qemu_st address, data_reg */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffffu; + ct->regs = 0xffffffffu; #ifdef CONFIG_SOFTMMU /* x0 and x1 will be overwritten when reading the tlb entry, and x2, and x3 for helper args, better to avoid using them. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3); + tcg_regset_reset_reg(ct->regs, TCG_REG_X0); + tcg_regset_reset_reg(ct->regs, TCG_REG_X1); + tcg_regset_reset_reg(ct->regs, TCG_REG_X2); + tcg_regset_reset_reg(ct->regs, TCG_REG_X3); #endif break; case 'A': /* Valid for arithmetic immediate (positive or negative). */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index bc1e1b5a71..978eb1dd70 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -254,40 +254,40 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; + ct->regs = 0xffff; break; /* qemu_ld address */ case 'l': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; + ct->regs = 0xffff; #ifdef CONFIG_SOFTMMU /* r0-r2,lr will be overwritten when reading the tlb entry, so don't use these. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); + tcg_regset_reset_reg(ct->regs, TCG_REG_R0); + tcg_regset_reset_reg(ct->regs, TCG_REG_R1); + tcg_regset_reset_reg(ct->regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->regs, TCG_REG_R14); #endif break; /* qemu_st address & data */ case 's': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; + ct->regs = 0xffff; /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) and r0-r1 doing the byte swapping, so don't use these. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); + tcg_regset_reset_reg(ct->regs, TCG_REG_R0); + tcg_regset_reset_reg(ct->regs, TCG_REG_R1); #if defined(CONFIG_SOFTMMU) /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->regs, TCG_REG_R2); #if TARGET_LONG_BITS == 64 /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #endif - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); + tcg_regset_reset_reg(ct->regs, TCG_REG_R14); #endif break; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 0155c0691c..8661ec3393 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -209,42 +209,42 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch(*ct_str++) { case 'a': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); + tcg_regset_set_reg(ct->regs, TCG_REG_EAX); break; case 'b': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); + tcg_regset_set_reg(ct->regs, TCG_REG_EBX); break; case 'c': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); + tcg_regset_set_reg(ct->regs, TCG_REG_ECX); break; case 'd': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); + tcg_regset_set_reg(ct->regs, TCG_REG_EDX); break; case 'S': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); + tcg_regset_set_reg(ct->regs, TCG_REG_ESI); break; case 'D': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); + tcg_regset_set_reg(ct->regs, TCG_REG_EDI); break; case 'q': /* A register that can be used as a byte operand. */ ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; + ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; break; case 'Q': /* A register with an addressable second byte (e.g. %ah). */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xf; + ct->regs = 0xf; break; case 'r': /* A general register. */ ct->ct |= TCG_CT_REG; - ct->u.regs |= ALL_GENERAL_REGS; + ct->regs |= ALL_GENERAL_REGS; break; case 'W': /* With TZCNT/LZCNT, we can have operand-size as an input. */ @@ -253,15 +253,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'x': /* A vector register. */ ct->ct |= TCG_CT_REG; - ct->u.regs |= ALL_VECTOR_REGS; + ct->regs |= ALL_VECTOR_REGS; break; /* qemu_ld/st address constraint */ case 'L': ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); + ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; + tcg_regset_reset_reg(ct->regs, TCG_REG_L0); + tcg_regset_reset_reg(ct->regs, TCG_REG_L1); break; case 'e': diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index bd5b8e09a0..d49a02bb03 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -196,28 +196,28 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch(*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; break; case 'L': /* qemu_ld input arg constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); + ct->regs = 0xffffffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); + tcg_regset_reset_reg(ct->regs, TCG_REG_A2); } #endif break; case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); + ct->regs = 0xffffffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3); + tcg_regset_reset_reg(ct->regs, TCG_REG_A2); + tcg_regset_reset_reg(ct->regs, TCG_REG_A3); } else { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1); + tcg_regset_reset_reg(ct->regs, TCG_REG_A1); } #endif break; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 393c4b30e0..450b555522 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -225,33 +225,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'A': case 'B': case 'C': case 'D': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); + tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A'); break; case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; break; case 'v': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff00000000ull; + ct->regs = 0xffffffff00000000ull; break; case 'L': /* qemu_ld constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + ct->regs = 0xffffffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); + tcg_regset_reset_reg(ct->regs, TCG_REG_R4); + tcg_regset_reset_reg(ct->regs, TCG_REG_R5); #endif break; case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + ct->regs = 0xffffffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); + tcg_regset_reset_reg(ct->regs, TCG_REG_R4); + tcg_regset_reset_reg(ct->regs, TCG_REG_R5); + tcg_regset_reset_reg(ct->regs, TCG_REG_R6); #endif break; case 'I': diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2dfb07e247..0a69839adb 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -138,19 +138,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; break; case 'L': /* qemu_ld/qemu_st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ #if defined(CONFIG_SOFTMMU) - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]); + tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]); #endif break; case 'I': diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 985115acfb..9cd266a2d0 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -409,24 +409,24 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': /* all registers */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; + ct->regs = 0xffff; break; case 'L': /* qemu_ld/st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); + ct->regs = 0xffff; + tcg_regset_reset_reg(ct->regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->regs, TCG_REG_R4); break; case 'a': /* force R2 for division */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0; - tcg_regset_set_reg(ct->u.regs, TCG_REG_R2); + ct->regs = 0; + tcg_regset_set_reg(ct->regs, TCG_REG_R2); break; case 'b': /* force R3 for division */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0; - tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); + ct->regs = 0; + tcg_regset_set_reg(ct->regs, TCG_REG_R3); break; case 'A': ct->ct |= TCG_CT_CONST_S33; diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 0f1d91fc21..c662293fc7 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -326,27 +326,27 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; break; case 'R': ct->ct |= TCG_CT_REG; - ct->u.regs = ALL_64; + ct->regs = ALL_64; break; case 'A': /* qemu_ld/st address constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; + ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; reserve_helpers: - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); + tcg_regset_reset_reg(ct->regs, TCG_REG_O0); + tcg_regset_reset_reg(ct->regs, TCG_REG_O1); + tcg_regset_reset_reg(ct->regs, TCG_REG_O2); break; case 's': /* qemu_st data 32-bit constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; + ct->regs = 0xffffffff; goto reserve_helpers; case 'S': /* qemu_st data 64-bit constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = ALL_64; + ct->regs = ALL_64; goto reserve_helpers; case 'I': ct->ct |= TCG_CT_CONST_S11; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 992d50cb1e..a7215f346f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -393,7 +393,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'L': /* qemu_ld constraint */ case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; - ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; + ct->regs = BIT(TCG_TARGET_NB_REGS) - 1; break; default: return NULL;

[02/43] tcg: Drop union from TCGArgConstraint

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