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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These values are constant, and are derived from the other configuration knobs. Move them into MicroBlazeCPUConfig to emphasize that they are not variable. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 5 +- hw/microblaze/petalogix_ml605_mmu.c | 6 +- target/microblaze/cpu.c | 92 ++++++++++++++--------------- target/microblaze/gdbstub.c | 4 +- target/microblaze/helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 3 +- 7 files changed, 54 insertions(+), 60 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 4d53345f23..ef96f2fe02 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -285,10 +285,6 @@ struct CPUMBState { struct {} end_reset_fields; /* These fields are preserved on reset. */ - - struct { - uint32_t regs[13]; - } pvr; }; /* @@ -301,6 +297,7 @@ typedef struct { uint32_t base_vectors; uint32_t pvr_user2; + uint32_t pvr_regs[13]; uint8_t addr_size; uint8_t use_fpu; diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index e49fc86eb8..159db6cbe2 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -200,9 +200,9 @@ petalogix_ml605_init(MachineState *machine) } /* setup PVR to match kernel settings */ - cpu->env.pvr.regs[4] = 0xc56b8000; - cpu->env.pvr.regs[5] = 0xc56be000; - cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */ + cpu->cfg.pvr_regs[4] = 0xc56b8000; + cpu->cfg.pvr_regs[5] = 0xc56be000; + cpu->cfg.pvr_regs[10] = 0x0e000000; /* virtex 6 */ microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size, machine->initrd_filename, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6392524135..b9bb7f0cc7 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -153,7 +153,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) CPUState *cs = CPU(dev); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; uint8_t version_code = 0; const char *version; int i = 0; @@ -173,16 +172,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_EXC_MASK - | PVR0_USE_ICACHE_MASK - | PVR0_USE_DCACHE_MASK; - env->pvr.regs[2] = PVR2_D_OPB_MASK - | PVR2_D_LMB_MASK - | PVR2_I_OPB_MASK - | PVR2_I_LMB_MASK - | PVR2_FPU_EXC_MASK - | 0; - version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; for (i = 0; mb_cpu_lookup[i].name && version; i++) { if (strcmp(mb_cpu_lookup[i].name, version) == 0) { @@ -195,46 +184,53 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); } - env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | - (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | - (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | - (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | - (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | - (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | - (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | - (version_code << PVR0_VERSION_SHIFT) | - (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | - cpu->cfg.pvr_user1; + cpu->cfg.pvr_regs[0] = + (PVR0_USE_EXC_MASK | + PVR0_USE_ICACHE_MASK | + PVR0_USE_DCACHE_MASK | + (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | + (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | + (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | + (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | + (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | + (version_code << PVR0_VERSION_SHIFT) | + (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | + cpu->cfg.pvr_user1); - env->pvr.regs[1] = cpu->cfg.pvr_user2; - env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | - (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | - (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | - (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | - (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | - (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | - (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | - (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | - (cpu->cfg.dopb_bus_exception ? - PVR2_DOPB_BUS_EXC_MASK : 0) | - (cpu->cfg.iopb_bus_exception ? - PVR2_IOPB_BUS_EXC_MASK : 0) | - (cpu->cfg.div_zero_exception ? - PVR2_DIV_ZERO_EXC_MASK : 0) | - (cpu->cfg.illegal_opcode_exception ? - PVR2_ILL_OPCODE_EXC_MASK : 0) | - (cpu->cfg.unaligned_exceptions ? - PVR2_UNALIGNED_EXC_MASK : 0) | - (cpu->cfg.opcode_0_illegal ? - PVR2_OPCODE_0x0_ILL_MASK : 0); + cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2; - env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? - PVR5_DCACHE_WRITEBACK_MASK : 0; + cpu->cfg.pvr_regs[2] = + (PVR2_D_OPB_MASK | + PVR2_D_LMB_MASK | + PVR2_I_OPB_MASK | + PVR2_I_LMB_MASK | + PVR2_FPU_EXC_MASK | + (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | + (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | + (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | + (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | + (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | + (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | + (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) | + (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) | + (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) | + (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0)); - env->pvr.regs[10] = 0x0c000000 | /* Default to spartan 3a dsp family. */ - (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT; - env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | - 16 << 17; + cpu->cfg.pvr_regs[5] |= + cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; + + cpu->cfg.pvr_regs[10] = + (0x0c000000 | /* Default to spartan 3a dsp family. */ + (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT); + + cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | + 16 << 17); mcc->parent_realize(dev, errp); } diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 08d6a0e807..9e3b9ac824 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -78,7 +78,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - val = env->pvr.regs[n - GDB_PVR0]; + val = cpu->cfg.pvr_regs[n - GDB_PVR0]; break; case GDB_EDR: val = env->edr; @@ -134,7 +134,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - env->pvr.regs[n - GDB_PVR0] = tmp; + cpu->cfg.pvr_regs[n - GDB_PVR0] = tmp; break; case GDB_EDR: env->edr = tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 3c2fd388fb..c9f236c897 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -122,7 +122,7 @@ void mb_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_HW_EXCP: - if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { + if (!(cpu->cfg.pvr_regs[0] & PVR0_USE_EXC_MASK)) { qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n"); return; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 4614e99db3..757f3ff04b 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -134,7 +134,7 @@ static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) raise = 1; } if (raise - && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) + && (env_archcpu(env)->cfg.pvr_regs[2] & PVR2_FPU_EXC_MASK) && (env->msr & MSR_EE)) { raise_fpu_exception(env, ra); } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ff0cb7dbb6..9e4551d99b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1539,7 +1539,8 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg) case 0x2000 ... 0x200c: tcg_gen_ld_i32(dest, cpu_env, - offsetof(CPUMBState, pvr.regs[arg->rs - 0x2000])); + offsetof(MicroBlazeCPU, cfg.pvr_regs[arg->rs - 0x2000]) + - offsetof(MicroBlazeCPU, env)); break; default: qemu_log_mask(LOG_GUEST_ERROR, "Invalid mfs reg 0x%x\n", arg->rs);