From patchwork Mon Aug 31 16:05:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248773 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp3448428ilg; Mon, 31 Aug 2020 09:16:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQbkpBqOizFe+npqUhBMNKCUe6QosmucXVfSVMqio+8+pX79LiMi4HOfT6n2spG8J0uuPC X-Received: by 2002:a25:2612:: with SMTP id m18mr3336154ybm.184.1598890586391; Mon, 31 Aug 2020 09:16:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598890586; cv=none; d=google.com; s=arc-20160816; b=CojfUu1MFo07Wnv7+uobTz3zPdYIHmsI7zww9qAr+QX2114yJBXP2KtRt5loGj2RFn 43LzxlkwIWCX6h8YHI6/gS6FxyfTp2BIMiVn059iAv5S+U5xcJo8apDxgDD3Ktin+AAy wNDRJPYtZd0/esGtktfZ7XV6lHMDh6vmw4DFl7Dc5DCGFs9VivpXNZx0xIzekLNSA63N JfMmMij9kD6DanI5/mrgUz0JBJFn+FoAKr+yl9yQmL/MdDkPLuaDOmhqmQKuf1o7hbIE J+kJiFqEv8aD5s/IkQmH2qRCvirhYi5JXDs6lLggNGaC9RbT+mqHN77ZXUvwyeIDj9+W smHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=haB+kLrfuYUnX1QRhCRrExdmXpWhe0msojEhc/6IfBE=; b=AXVucuNqebujc7ua6TSQgySJFGpIK8YNE1pGLzCpxozQ9rDwC5knI/ecvIjnGEuI6a zXo1Eg30bKDZlgi3YHWcQBJPanKUim5IoblcgtONtQarLU2zewekfXF7QvniFOLeB+sM LcPmO5dwd3N0qKtJMt2Hy2/+Qy6z8bGgVrFkQp9+/41HIRCK5F+YXHTqJuf0N3hzJMUH XstVa9Edf22NqzEVo+APPk9BnN9OHcYTz9+hjFWFMNCECofIBRQuD4UV6/tzA3WCUHuz //V5n0Ta7Dq5hwbh7lEfaVtv3MEAGRpnA3qJOrKZt9u731bs6s8sep88wZGoyJpC/QWv D2Ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q+k2ihij; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x18si8076519ybl.361.2020.08.31.09.16.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Aug 2020 09:16:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q+k2ihij; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCmTp-0006hE-St for patch@linaro.org; Mon, 31 Aug 2020 12:16:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCmKD-00042l-Tc for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:29 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:35329) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCmKC-0005xr-3V for qemu-devel@nongnu.org; Mon, 31 Aug 2020 12:06:29 -0400 Received: by mail-pj1-x1030.google.com with SMTP id g6so31883pjl.0 for ; Mon, 31 Aug 2020 09:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=haB+kLrfuYUnX1QRhCRrExdmXpWhe0msojEhc/6IfBE=; b=Q+k2ihijyVPVWPtuvJ/wbicUttguv37ghqruVnOwXXEtxnNXmRf5wXaDKsvQHxvGBe ggBi+2QAJo05a+m08rnNA+52jv0W9eFZHop8Z16zVPyM0v+SEcMmbtEMqALrnIFkF4X6 G22xvi7F7ZxL7+3EeHaKS3VDF1klgkSZraNYkoLS5217Vped4dtCT8u8aHXa03aDaXTg EJ8nMng8b2KapHZEejCo3oOpDI1e7ePje6fY2nU6r5j7bg9q/vF9NQse3Uniw8EkYVZP itl9Nh5/tJtX4vY9FccPck8TeRhv8YklCCESEmGNfqhfeaQ0vqo3XpspcSr15H7HOmk0 1eBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=haB+kLrfuYUnX1QRhCRrExdmXpWhe0msojEhc/6IfBE=; b=AMZ8XWnSFxx9peKn4OzBpbpOowoi3MRnq54+HAXZrU22es73nK60JjuZGyOwsNfiGw GQsjoR4M68d9erc9+1MzEK58KZUoxbsHVgg3FSa686bgqPol3RgkQ5krbAxjwYQkHCl8 G5gcWfCjPw12K0uSYp0JB9zJtd4Ft3F22rGuAR+MJqRqDrPYn2YhVrEed12hijpQO4Ov jpkyPH23s80LVGpfyDaz023JQ+n2rv+cko3ZzFfx7kd6qRlt+RknkkeNH1VCCi3VJAJZ ehOFTYY1cjT34ODEalfOt5mvBZtlOwil7VaI112r58eW1nrIT9wnE/qY2pEiPNC9xv+i CXcQ== X-Gm-Message-State: AOAM530R8jCdFCLz1/KL7LLJt3uFOd5iYpaWkvo4OwK1cR0hJbuHnEiU A7XXmH7rwL6e48jAEE2s5TCiHzt8Fxu3bg== X-Received: by 2002:a17:90a:7e15:: with SMTP id i21mr57021pjl.175.1598889986167; Mon, 31 Aug 2020 09:06:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id gt13sm17218pjb.43.2020.08.31.09.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 09:06:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 16/76] target/microblaze: Fix width of FSR Date: Mon, 31 Aug 2020 09:05:01 -0700 Message-Id: <20200831160601.833692-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org> References: <20200831160601.833692-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_fsr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index aaac0c9a6c..34177f9b28 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,7 +240,7 @@ struct CPUMBState { uint32_t msr; uint64_t ear; uint32_t esr; - uint64_t fsr; + uint32_t fsr; uint64_t btr; uint64_t edr; float_status fp_status; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f63aae6de9..3fc2feda3d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; @@ -542,7 +541,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); @@ -583,7 +583,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); @@ -1798,7 +1799,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " + "debug=%x imm=%x iflags=%x fsr=%x " "rbtr=%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, @@ -1867,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_fsr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr =