diff mbox series

[v2,07/76] target/microblaze: Split out EAR from env->sregs

Message ID 20200828141929.77854-8-richard.henderson@linaro.org
State Superseded
Headers show
Series target/microblaze improvements | expand

Commit Message

Richard Henderson Aug. 28, 2020, 2:18 p.m. UTC 
Continue eliminating the sregs array in favor of individual members.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/microblaze/cpu.h       | 1 +
 target/microblaze/gdbstub.c   | 4 ++--
 target/microblaze/helper.c    | 6 +++---
 target/microblaze/op_helper.c | 8 ++++----
 target/microblaze/translate.c | 6 ++++--
 5 files changed, 14 insertions(+), 11 deletions(-)

-- 
2.25.1

Comments

Philippe Mathieu-Daudé Aug. 31, 2020, 8:50 p.m. UTC | #1 
Le ven. 28 août 2020 16:23, Richard Henderson <richard.henderson@linaro.org>
a écrit :

> Continue eliminating the sregs array in favor of individual members.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


---
>  target/microblaze/cpu.h       | 1 +

>  target/microblaze/gdbstub.c   | 4 ++--

>  target/microblaze/helper.c    | 6 +++---

>  target/microblaze/op_helper.c | 8 ++++----

>  target/microblaze/translate.c | 6 ++++--

>  5 files changed, 14 insertions(+), 11 deletions(-)

>

> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h

> index 36de61d9f9..c9035b410e 100644

> --- a/target/microblaze/cpu.h

> +++ b/target/microblaze/cpu.h

> @@ -238,6 +238,7 @@ struct CPUMBState {

>      uint32_t regs[32];

>      uint64_t pc;

>      uint64_t msr;

> +    uint64_t ear;

>      uint64_t sregs[14];

>      float_status fp_status;

>      /* Stack protectors. Yes, it's a hw feature.  */

> diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c

> index e4c4936a7a..e33a613efe 100644

> --- a/target/microblaze/gdbstub.c

> +++ b/target/microblaze/gdbstub.c

> @@ -65,7 +65,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray

> *mem_buf, int n)

>          val = env->msr;

>          break;

>      case GDB_EAR:

> -        val = env->sregs[SR_EAR];

> +        val = env->ear;

>          break;

>      case GDB_ESR:

>          val = env->sregs[SR_ESR];

> @@ -121,7 +121,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t

> *mem_buf, int n)

>          env->msr = tmp;

>          break;

>      case GDB_EAR:

> -        env->sregs[SR_EAR] = tmp;

> +        env->ear = tmp;

>          break;

>      case GDB_ESR:

>          env->sregs[SR_ESR] = tmp;

> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c

> index a18314540f..afe9634781 100644

> --- a/target/microblaze/helper.c

> +++ b/target/microblaze/helper.c

> @@ -85,7 +85,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int

> size,

>      qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",

>                    mmu_idx, address);

>

> -    env->sregs[SR_EAR] = address;

> +    env->ear = address;

>      switch (lu.err) {

>      case ERR_PROT:

>          env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16;

> @@ -145,7 +145,7 @@ void mb_cpu_do_interrupt(CPUState *cs)

>              qemu_log_mask(CPU_LOG_INT,

>                            "hw exception at pc=%" PRIx64 " ear=%" PRIx64 "

> "

>                            "esr=%" PRIx64 " iflags=%x\n",

> -                          env->pc, env->sregs[SR_EAR],

> +                          env->pc, env->ear,

>                            env->sregs[SR_ESR], env->iflags);

>              log_cpu_state_mask(CPU_LOG_INT, cs, 0);

>              env->iflags &= ~(IMM_FLAG | D_FLAG);

> @@ -188,7 +188,7 @@ void mb_cpu_do_interrupt(CPUState *cs)

>              qemu_log_mask(CPU_LOG_INT,

>                            "exception at pc=%" PRIx64 " ear=%" PRIx64 " "

>                            "iflags=%x\n",

> -                          env->pc, env->sregs[SR_EAR], env->iflags);

> +                          env->pc, env->ear, env->iflags);

>              log_cpu_state_mask(CPU_LOG_INT, cs, 0);

>              env->iflags &= ~(IMM_FLAG | D_FLAG);

>              env->pc = cpu->cfg.base_vectors + 0x20;

> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c

> index 3668382d36..5bacd29663 100644

> --- a/target/microblaze/op_helper.c

> +++ b/target/microblaze/op_helper.c

> @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env)

>      qemu_log("PC=%" PRIx64 "\n", env->pc);

>      qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "

>               "debug[%x] imm=%x iflags=%x\n",

> -             env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR],

> +             env->msr, env->sregs[SR_ESR], env->ear,

>               env->debug, env->imm, env->iflags);

>      qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d

> ie=%d\n",

>               env->btaken, env->btarget,

> @@ -431,7 +431,7 @@ void helper_memalign(CPUMBState *env, target_ulong

> addr,

>                            "unaligned access addr=" TARGET_FMT_lx

>                            " mask=%x, wr=%d dr=r%d\n",

>                            addr, mask, wr, dr);

> -            env->sregs[SR_EAR] = addr;

> +            env->ear = addr;

>              env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \

>                                   | (dr & 31) << 5;

>              if (mask == 3) {

> @@ -450,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong

> addr)

>          qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "

>                        TARGET_FMT_lx " %x %x\n",

>                        addr, env->slr, env->shr);

> -        env->sregs[SR_EAR] = addr;

> +        env->ear = addr;

>          env->sregs[SR_ESR] = ESR_EC_STACKPROT;

>          helper_raise_exception(env, EXCP_HW_EXCP);

>      }

> @@ -488,7 +488,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr

> physaddr, vaddr addr,

>          return;

>      }

>

> -    env->sregs[SR_EAR] = addr;

> +    env->ear = addr;

>      if (access_type == MMU_INST_FETCH) {

>          if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {

>              env->sregs[SR_ESR] = ESR_EC_INSN_BUS;

> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c

> index 9f2dcd82cd..62747b02f3 100644

> --- a/target/microblaze/translate.c

> +++ b/target/microblaze/translate.c

> @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int

> flags)

>      qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "

>                   "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "

>                   "rbtr=%" PRIx64 "\n",

> -                 env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR],

> +                 env->msr, env->sregs[SR_ESR], env->ear,

>                   env->debug, env->imm, env->iflags, env->sregs[SR_FSR],

>                   env->sregs[SR_BTR]);

>      qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "

> @@ -1873,8 +1873,10 @@ void mb_tcg_init(void)

>          tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc");

>      cpu_SR[SR_MSR] =

>          tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr),

> "rmsr");

> +    cpu_SR[SR_EAR] =

> +        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear),

> "rear");

>

> -    for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {

> +    for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) {

>          cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,

>                            offsetof(CPUMBState, sregs[i]),

>                            special_regnames[i]);

> --

> 2.25.1

>

>

>
<div dir="auto"><div><br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">Le ven. 28 août 2020 16:23, Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>&gt; a écrit :<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Continue eliminating the sregs array in favor of individual members.<br>
<br>
Signed-off-by: Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org" target="_blank" rel="noreferrer">richard.henderson@linaro.org</a>&gt;<br></blockquote></div></div><div dir="auto"><br></div><div dir="auto"><span style="font-family:sans-serif;font-size:13.696px">Reviewed-by: Philippe Mathieu-Daudé &lt;</span><a href="mailto:f4bug@amsat.org" style="text-decoration:none;color:rgb(66,133,244);font-family:sans-serif;font-size:13.696px">f4bug@amsat.org</a><span style="font-family:sans-serif;font-size:13.696px">&gt;</span><br></div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">

---<br>
 target/microblaze/cpu.h       | 1 +<br>
 target/microblaze/gdbstub.c   | 4 ++--<br>
 target/microblaze/helper.c    | 6 +++---<br>
 target/microblaze/op_helper.c | 8 ++++----<br>
 target/microblaze/translate.c | 6 ++++--<br>
 5 files changed, 14 insertions(+), 11 deletions(-)<br>
<br>
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h<br>
index 36de61d9f9..c9035b410e 100644<br>
--- a/target/microblaze/cpu.h<br>
+++ b/target/microblaze/cpu.h<br>
@@ -238,6 +238,7 @@ struct CPUMBState {<br>
     uint32_t regs[32];<br>
     uint64_t pc;<br>
     uint64_t msr;<br>
+    uint64_t ear;<br>
     uint64_t sregs[14];<br>
     float_status fp_status;<br>
     /* Stack protectors. Yes, it&#39;s a hw feature.  */<br>
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c<br>
index e4c4936a7a..e33a613efe 100644<br>
--- a/target/microblaze/gdbstub.c<br>
+++ b/target/microblaze/gdbstub.c<br>
@@ -65,7 +65,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)<br>
         val = env-&gt;msr;<br>
         break;<br>
     case GDB_EAR:<br>
-        val = env-&gt;sregs[SR_EAR];<br>
+        val = env-&gt;ear;<br>
         break;<br>
     case GDB_ESR:<br>
         val = env-&gt;sregs[SR_ESR];<br>
@@ -121,7 +121,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)<br>
         env-&gt;msr = tmp;<br>
         break;<br>
     case GDB_EAR:<br>
-        env-&gt;sregs[SR_EAR] = tmp;<br>
+        env-&gt;ear = tmp;<br>
         break;<br>
     case GDB_ESR:<br>
         env-&gt;sregs[SR_ESR] = tmp;<br>
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c<br>
index a18314540f..afe9634781 100644<br>
--- a/target/microblaze/helper.c<br>
+++ b/target/microblaze/helper.c<br>
@@ -85,7 +85,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,<br>
     qemu_log_mask(CPU_LOG_MMU, &quot;mmu=%d miss v=%&quot; VADDR_PRIx &quot;\n&quot;,<br>
                   mmu_idx, address);<br>
<br>
-    env-&gt;sregs[SR_EAR] = address;<br>
+    env-&gt;ear = address;<br>
     switch (lu.err) {<br>
     case ERR_PROT:<br>
         env-&gt;sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16;<br>
@@ -145,7 +145,7 @@ void mb_cpu_do_interrupt(CPUState *cs)<br>
             qemu_log_mask(CPU_LOG_INT,<br>
                           &quot;hw exception at pc=%&quot; PRIx64 &quot; ear=%&quot; PRIx64 &quot; &quot;<br>
                           &quot;esr=%&quot; PRIx64 &quot; iflags=%x\n&quot;,<br>
-                          env-&gt;pc, env-&gt;sregs[SR_EAR],<br>
+                          env-&gt;pc, env-&gt;ear,<br>
                           env-&gt;sregs[SR_ESR], env-&gt;iflags);<br>
             log_cpu_state_mask(CPU_LOG_INT, cs, 0);<br>
             env-&gt;iflags &amp;= ~(IMM_FLAG | D_FLAG);<br>
@@ -188,7 +188,7 @@ void mb_cpu_do_interrupt(CPUState *cs)<br>
             qemu_log_mask(CPU_LOG_INT,<br>
                           &quot;exception at pc=%&quot; PRIx64 &quot; ear=%&quot; PRIx64 &quot; &quot;<br>
                           &quot;iflags=%x\n&quot;,<br>
-                          env-&gt;pc, env-&gt;sregs[SR_EAR], env-&gt;iflags);<br>
+                          env-&gt;pc, env-&gt;ear, env-&gt;iflags);<br>
             log_cpu_state_mask(CPU_LOG_INT, cs, 0);<br>
             env-&gt;iflags &amp;= ~(IMM_FLAG | D_FLAG);<br>
             env-&gt;pc = cpu-&gt;cfg.base_vectors + 0x20;<br>
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c<br>
index 3668382d36..5bacd29663 100644<br>
--- a/target/microblaze/op_helper.c<br>
+++ b/target/microblaze/op_helper.c<br>
@@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env)<br>
     qemu_log(&quot;PC=%&quot; PRIx64 &quot;\n&quot;, env-&gt;pc);<br>
     qemu_log(&quot;rmsr=%&quot; PRIx64 &quot; resr=%&quot; PRIx64 &quot; rear=%&quot; PRIx64 &quot; &quot;<br>
              &quot;debug[%x] imm=%x iflags=%x\n&quot;,<br>
-             env-&gt;msr, env-&gt;sregs[SR_ESR], env-&gt;sregs[SR_EAR],<br>
+             env-&gt;msr, env-&gt;sregs[SR_ESR], env-&gt;ear,<br>
              env-&gt;debug, env-&gt;imm, env-&gt;iflags);<br>
     qemu_log(&quot;btaken=%d btarget=%&quot; PRIx64 &quot; mode=%s(saved=%s) eip=%d ie=%d\n&quot;,<br>
              env-&gt;btaken, env-&gt;btarget,<br>
@@ -431,7 +431,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr,<br>
                           &quot;unaligned access addr=&quot; TARGET_FMT_lx<br>
                           &quot; mask=%x, wr=%d dr=r%d\n&quot;,<br>
                           addr, mask, wr, dr);<br>
-            env-&gt;sregs[SR_EAR] = addr;<br>
+            env-&gt;ear = addr;<br>
             env-&gt;sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr &lt;&lt; 10) \<br>
                                  | (dr &amp; 31) &lt;&lt; 5;<br>
             if (mask == 3) {<br>
@@ -450,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)<br>
         qemu_log_mask(CPU_LOG_INT, &quot;Stack protector violation at &quot;<br>
                       TARGET_FMT_lx &quot; %x %x\n&quot;,<br>
                       addr, env-&gt;slr, env-&gt;shr);<br>
-        env-&gt;sregs[SR_EAR] = addr;<br>
+        env-&gt;ear = addr;<br>
         env-&gt;sregs[SR_ESR] = ESR_EC_STACKPROT;<br>
         helper_raise_exception(env, EXCP_HW_EXCP);<br>
     }<br>
@@ -488,7 +488,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,<br>
         return;<br>
     }<br>
<br>
-    env-&gt;sregs[SR_EAR] = addr;<br>
+    env-&gt;ear = addr;<br>
     if (access_type == MMU_INST_FETCH) {<br>
         if ((env-&gt;pvr.regs[2] &amp; PVR2_IOPB_BUS_EXC_MASK)) {<br>
             env-&gt;sregs[SR_ESR] = ESR_EC_INSN_BUS;<br>
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c<br>
index 9f2dcd82cd..62747b02f3 100644<br>
--- a/target/microblaze/translate.c<br>
+++ b/target/microblaze/translate.c<br>
@@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)<br>
     qemu_fprintf(f, &quot;rmsr=%&quot; PRIx64 &quot; resr=%&quot; PRIx64 &quot; rear=%&quot; PRIx64 &quot; &quot;<br>
                  &quot;debug=%x imm=%x iflags=%x fsr=%&quot; PRIx64 &quot; &quot;<br>
                  &quot;rbtr=%&quot; PRIx64 &quot;\n&quot;,<br>
-                 env-&gt;msr, env-&gt;sregs[SR_ESR], env-&gt;sregs[SR_EAR],<br>
+                 env-&gt;msr, env-&gt;sregs[SR_ESR], env-&gt;ear,<br>
                  env-&gt;debug, env-&gt;imm, env-&gt;iflags, env-&gt;sregs[SR_FSR],<br>
                  env-&gt;sregs[SR_BTR]);<br>
     qemu_fprintf(f, &quot;btaken=%d btarget=%&quot; PRIx64 &quot; mode=%s(saved=%s) &quot;<br>
@@ -1873,8 +1873,10 @@ void mb_tcg_init(void)<br>
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), &quot;rpc&quot;);<br>
     cpu_SR[SR_MSR] =<br>
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), &quot;rmsr&quot;);<br>
+    cpu_SR[SR_EAR] =<br>
+        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), &quot;rear&quot;);<br>
<br>
-    for (i = SR_MSR + 1; i &lt; ARRAY_SIZE(cpu_SR); i++) {<br>
+    for (i = SR_EAR + 1; i &lt; ARRAY_SIZE(cpu_SR); i++) {<br>
         cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,<br>
                           offsetof(CPUMBState, sregs[i]),<br>
                           special_regnames[i]);<br>
-- <br>
2.25.1<br>
<br>
<br>
</blockquote></div></div></div>
diff mbox series

Patch

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 36de61d9f9..c9035b410e 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -238,6 +238,7 @@  struct CPUMBState {
     uint32_t regs[32];
     uint64_t pc;
     uint64_t msr;
+    uint64_t ear;
     uint64_t sregs[14];
     float_status fp_status;
     /* Stack protectors. Yes, it's a hw feature.  */
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index e4c4936a7a..e33a613efe 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -65,7 +65,7 @@  int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
         val = env->msr;
         break;
     case GDB_EAR:
-        val = env->sregs[SR_EAR];
+        val = env->ear;
         break;
     case GDB_ESR:
         val = env->sregs[SR_ESR];
@@ -121,7 +121,7 @@  int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
         env->msr = tmp;
         break;
     case GDB_EAR:
-        env->sregs[SR_EAR] = tmp;
+        env->ear = tmp;
         break;
     case GDB_ESR:
         env->sregs[SR_ESR] = tmp;
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index a18314540f..afe9634781 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -85,7 +85,7 @@  bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
                   mmu_idx, address);
 
-    env->sregs[SR_EAR] = address;
+    env->ear = address;
     switch (lu.err) {
     case ERR_PROT:
         env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16;
@@ -145,7 +145,7 @@  void mb_cpu_do_interrupt(CPUState *cs)
             qemu_log_mask(CPU_LOG_INT,
                           "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
                           "esr=%" PRIx64 " iflags=%x\n",
-                          env->pc, env->sregs[SR_EAR],
+                          env->pc, env->ear,
                           env->sregs[SR_ESR], env->iflags);
             log_cpu_state_mask(CPU_LOG_INT, cs, 0);
             env->iflags &= ~(IMM_FLAG | D_FLAG);
@@ -188,7 +188,7 @@  void mb_cpu_do_interrupt(CPUState *cs)
             qemu_log_mask(CPU_LOG_INT,
                           "exception at pc=%" PRIx64 " ear=%" PRIx64 " "
                           "iflags=%x\n",
-                          env->pc, env->sregs[SR_EAR], env->iflags);
+                          env->pc, env->ear, env->iflags);
             log_cpu_state_mask(CPU_LOG_INT, cs, 0);
             env->iflags &= ~(IMM_FLAG | D_FLAG);
             env->pc = cpu->cfg.base_vectors + 0x20;
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 3668382d36..5bacd29663 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -78,7 +78,7 @@  void helper_debug(CPUMBState *env)
     qemu_log("PC=%" PRIx64 "\n", env->pc);
     qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
              "debug[%x] imm=%x iflags=%x\n",
-             env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR],
+             env->msr, env->sregs[SR_ESR], env->ear,
              env->debug, env->imm, env->iflags);
     qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n",
              env->btaken, env->btarget,
@@ -431,7 +431,7 @@  void helper_memalign(CPUMBState *env, target_ulong addr,
                           "unaligned access addr=" TARGET_FMT_lx
                           " mask=%x, wr=%d dr=r%d\n",
                           addr, mask, wr, dr);
-            env->sregs[SR_EAR] = addr;
+            env->ear = addr;
             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                  | (dr & 31) << 5;
             if (mask == 3) {
@@ -450,7 +450,7 @@  void helper_stackprot(CPUMBState *env, target_ulong addr)
         qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "
                       TARGET_FMT_lx " %x %x\n",
                       addr, env->slr, env->shr);
-        env->sregs[SR_EAR] = addr;
+        env->ear = addr;
         env->sregs[SR_ESR] = ESR_EC_STACKPROT;
         helper_raise_exception(env, EXCP_HW_EXCP);
     }
@@ -488,7 +488,7 @@  void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
         return;
     }
 
-    env->sregs[SR_EAR] = addr;
+    env->ear = addr;
     if (access_type == MMU_INST_FETCH) {
         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 9f2dcd82cd..62747b02f3 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1809,7 +1809,7 @@  void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
                  "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
                  "rbtr=%" PRIx64 "\n",
-                 env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR],
+                 env->msr, env->sregs[SR_ESR], env->ear,
                  env->debug, env->imm, env->iflags, env->sregs[SR_FSR],
                  env->sregs[SR_BTR]);
     qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
@@ -1873,8 +1873,10 @@  void mb_tcg_init(void)
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc");
     cpu_SR[SR_MSR] =
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr");
+    cpu_SR[SR_EAR] =
+        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
 
-    for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
+    for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
         cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
                           offsetof(CPUMBState, sregs[i]),
                           special_regnames[i]);