From patchwork Fri Aug 28 14:19:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248569 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp1144745ilg; Fri, 28 Aug 2020 07:46:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJxtkWH0JtRySRy367uC8Ubphy1t5OeCpPKyb1GOvyWzeZRf5D83VzKBRWktvMQHoNa4sU X-Received: by 2002:a25:9885:: with SMTP id l5mr3202298ybo.0.1598626002529; Fri, 28 Aug 2020 07:46:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598626002; cv=none; d=google.com; s=arc-20160816; b=rN489vJ+jEweE5CdRlYUR98HBpKmUgR72D/xWXd5gDbI/BEXbtFwPpkn2QBA9GccCd yfW/NieZMYSZorG0M/8UyoH8zH/elKF5ddaB9fsxSfw0WDDBTFRuO+slY4iOL7FKHdwq VT/gWqG/TiziVgeaagL8EUWg2x3bcBL69VBu4UlGlVnXkBge0+MpF3A8GjJ15//a/9Tj 9HbsNcUmXtvh1zNwXlIgI4aO4Z++/iXnNpXlI/jJXkEgGQUM4VfZT7Gcc4gKxJBOm0jK QWn61fMibfhzAO2hs6wWPecq0m/Equ8I8KV8QWsswcsxZ3xfNKt4KAMQaFtdMxu4UdUA 6/tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Se9V31A0uMu+OKiOdywcS9qj4QHTRgy+XhYVMdJ4PwY=; b=sof3G1z0qkdWlrV3oXlMFI6jX/33zQKa8hI8IO0xPr5YV/Q4gLV+KgjOfC7VJ74Ias dVSdym0gPukBUe1yQKzPH3jYQstcXYDJ8vH1WwkDpQ0/uPYn+hHjd4mGLVLw4bTy7zwJ cmSTicNChGBhMEqlv2Ygq6jL93fDFMKbwKZSXB/YcZ7TUNWcf8xX2qLD/GYR2cU+/arf S6wOvLMMykNdxJncIh+Qogfz3aLGVYeubdUwd2f8El5t5qHLcMtANrX8QiDB/tbUkIJZ cdcIyiSK07jTbN1k2aE/vwBTXc5KT4v4QhuXheab7nYHXXszTVWjyyVMqwKXb0U6AUyx uONw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p2GlibG+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o11si1181867ybm.201.2020.08.28.07.46.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Aug 2020 07:46:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p2GlibG+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBfeL-0003ff-Ta for patch@linaro.org; Fri, 28 Aug 2020 10:46:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBfFS-0002Hg-Le for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:58 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:36914) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kBfFQ-0005QH-8f for qemu-devel@nongnu.org; Fri, 28 Aug 2020 10:20:58 -0400 Received: by mail-pf1-x443.google.com with SMTP id x143so742734pfc.4 for ; Fri, 28 Aug 2020 07:20:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Se9V31A0uMu+OKiOdywcS9qj4QHTRgy+XhYVMdJ4PwY=; b=p2GlibG+XJG78a84DdCqox2ZkfSt/+a290C6Ji20Dw/0cgxBeMcXqLkbTB5GZS86vP IyFac/kdBvhgNNfMCNMspgn1bR53/oS6Mi0BdhRtFzbo0CzmIDjolY/g9lFSpmAQW80W sUY2v4ZA2/w+uP1pLnqaAMB4ZRH0SoO6dlhGxQlQl2wNcNrQRx7lEDczACUF8Y/o66C1 nYBbya9MZv6B/b0YVDgHsJf2or4LGsra8FAeaehn3m0x2VwmYeFDj0yOFp0KXMQie3yN 1Vc69yN+XquR3Hz0uj0UW0mSdn6zuKscJaN7bN+VXeEIdLNKXQNYf7UgHL+MYo2SLktw 1ocg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Se9V31A0uMu+OKiOdywcS9qj4QHTRgy+XhYVMdJ4PwY=; b=MCTMZRw5TvaYl3VG4/CKSQX89SrIum6B/WAsUfQwl8Dq2up93zOjYb5ipSweQaw4re 5/+xsC/HFNxkRdhC19X53O0G2AU3FJiHRLPjEO2btKws5pCK3lTu7rD4SdyxgrFsi0L6 ZF+0ZsLASqSQdrGaWfC2DtkU4AV5H6YLvo9XyWjWP7coUdFscxpKt22sQdPSfXFvhg6e jsB8GhKQC67swoxFs9ZWeGdxq1VONiY9FaOoTWyOg/ox4svsaoOZzuOetMseFLDQwmWj faXsJdEEYPl+3pNMS4HDGKIEu0lcEkceDNDa6X7yx+mE/k0fEyIHt1Fq5aJrmU9pOC8x /sAQ== X-Gm-Message-State: AOAM530D1akzqzh35gDyAdU68Yj4THHNSy7YwIk2C9a0dOblodW2vZoI p8EvZFUNYyblmR3OX0x4XfVcR58nn4TAPg== X-Received: by 2002:aa7:982e:: with SMTP id q14mr1471132pfl.299.1598624454378; Fri, 28 Aug 2020 07:20:54 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id j3sm1403080pjw.23.2020.08.28.07.20.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 07:20:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 65/76] target/microblaze: Reorganize branching Date: Fri, 28 Aug 2020 07:19:18 -0700 Message-Id: <20200828141929.77854-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200828141929.77854-1-richard.henderson@linaro.org> References: <20200828141929.77854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the btaken variable, and simplify things by always computing the full branch destination into btarget. This avoids all need for sync_jmpstate(). Retain the direct branch behaviour by remembering the jump destination in jmp_dest, discarding btarget. In the normal case, where the branch delay slot cannot trap (e.g. arithmetic not memory operation), tcg will remove the computation into btarget, leaving us with just the tcg direct branching at the end. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/translate.c | 192 ++++++++++++++-------------------- 2 files changed, 79 insertions(+), 117 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 1528749a0b..4298f242a6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -234,8 +234,8 @@ typedef struct CPUMBState CPUMBState; #define TARGET_INSN_START_EXTRA_WORDS 1 struct CPUMBState { - uint32_t btaken; - uint32_t btarget; + uint32_t bvalue; /* TCG temporary, only valid during a TB */ + uint32_t btarget; /* Full resolved branch destination */ uint32_t imm; uint32_t regs[32]; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 832cf85c64..1545974669 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -45,7 +45,7 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; -static TCGv_i32 cpu_btaken; +static TCGv_i32 cpu_bvalue; static TCGv_i32 cpu_btarget; static TCGv_i32 cpu_iflags; static TCGv cpu_res_addr; @@ -77,12 +77,11 @@ typedef struct DisasContext { unsigned int tb_flags_to_set; int mem_index; -#define JMP_NOJMP 0 -#define JMP_DIRECT 1 -#define JMP_DIRECT_CC 2 -#define JMP_INDIRECT 3 - unsigned int jmp; - uint32_t jmp_pc; + /* Condition under which to jump, including NEVER and ALWAYS. */ + TCGCond jmp_cond; + + /* Immediate branch-taken destination, or -1 for indirect. */ + uint32_t jmp_dest; int abort_at_next_insn; } DisasContext; @@ -106,17 +105,6 @@ static void t_sync_flags(DisasContext *dc) } } -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { - if (dc->jmp == JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp = tcg_const_i32(index); @@ -782,8 +770,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -885,8 +871,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - sync_jmpstate(dc); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); tcg_gen_mov_tl(cpu_res_addr, addr); tcg_temp_free(addr); @@ -920,8 +904,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, } } - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -1023,8 +1005,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) TCGLabel *swx_fail = gen_new_label(); TCGv_i32 tval; - sync_jmpstate(dc); - /* swx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); @@ -1392,44 +1372,6 @@ static void dec_msr(DisasContext *dc) } } -static inline void eval_cc(DisasContext *dc, unsigned int cc, - TCGv_i32 d, TCGv_i32 a) -{ - static const int mb_to_tcg_cc[] = { - [CC_EQ] = TCG_COND_EQ, - [CC_NE] = TCG_COND_NE, - [CC_LT] = TCG_COND_LT, - [CC_LE] = TCG_COND_LE, - [CC_GE] = TCG_COND_GE, - [CC_GT] = TCG_COND_GT, - }; - - switch (cc) { - case CC_EQ: - case CC_NE: - case CC_LT: - case CC_LE: - case CC_GE: - case CC_GT: - tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0); - break; - default: - cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); - break; - } -} - -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) -{ - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - cpu_btaken, zero, - pc_true, pc_false); - - tcg_temp_free_i32(zero); -} - static void dec_setup_dslot(DisasContext *dc) { dc->tb_flags_to_set |= D_FLAG; @@ -1440,8 +1382,17 @@ static void dec_setup_dslot(DisasContext *dc) static void dec_bcc(DisasContext *dc) { + static const TCGCond mb_to_tcg_cc[] = { + [CC_EQ] = TCG_COND_EQ, + [CC_NE] = TCG_COND_NE, + [CC_LT] = TCG_COND_LT, + [CC_LE] = TCG_COND_LE, + [CC_GE] = TCG_COND_GE, + [CC_GT] = TCG_COND_GT, + }; unsigned int cc; unsigned int dslot; + TCGv_i32 zero, next; cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); @@ -1450,15 +1401,29 @@ static void dec_bcc(DisasContext *dc) dec_setup_dslot(dc); } + dc->jmp_cond = mb_to_tcg_cc[cc]; + + /* Cache the condition register in cpu_bvalue across any delay slot. */ + tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); + + /* Store the branch taken destination into btarget. */ if (dc->type_b) { - dc->jmp = JMP_DIRECT_CC; - dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest = dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp = JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), + dc->base.pc_next); } - eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); + + /* Compute the final destination into btarget. */ + zero = tcg_const_i32(0); + next = tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, dc->ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); } static void dec_br(DisasContext *dc) @@ -1479,14 +1444,13 @@ static void dec_br(DisasContext *dc) add_pc = abs ? 0 : dc->base.pc_next; if (dc->type_b) { - dc->jmp = JMP_DIRECT; - dc->jmp_pc = add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest = add_pc + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp = JMP_INDIRECT; + dc->jmp_dest = -1; tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond = TCG_COND_ALWAYS; } static inline void do_rti(DisasContext *dc) @@ -1567,8 +1531,8 @@ static void dec_rts(DisasContext *dc) dc->tb_flags |= DRTE_FLAG; } - dc->jmp = JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond = TCG_COND_ALWAYS; + dc->jmp_dest = -1; tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } @@ -1659,13 +1623,14 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpu = cpu; dc->tb_flags = dc->base.tb->flags; - dc->jmp = dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; dc->mem_index = cpu_mmu_index(&cpu->env, false); + dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER; + dc->jmp_dest = -1; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1734,14 +1699,12 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags |= dc->tb_flags_to_set; dc->base.pc_next += 4; - if (dc->jmp != JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { + if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); - } - if (dc->tb_flags & DRTB_FLAG) { + } else if (dc->tb_flags & DRTB_FLAG) { do_rtb(dc); - } - if (dc->tb_flags & DRTE_FLAG) { + } else if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } dc->base.is_jmp = DISAS_JUMP; @@ -1766,19 +1729,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) } t_sync_flags(dc); - if (dc->tb_flags & D_FLAG) { - sync_jmpstate(dc); - dc->jmp = JMP_NOJMP; - } switch (dc->base.is_jmp) { case DISAS_TOO_MANY: - assert(dc->jmp == JMP_NOJMP); gen_goto_tb(dc, 0, dc->base.pc_next); return; case DISAS_UPDATE: - assert(dc->jmp == JMP_NOJMP); if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { @@ -1787,35 +1744,41 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) return; case DISAS_JUMP: - switch (dc->jmp) { - case JMP_INDIRECT: - { - TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); + if (dc->jmp_dest != -1 && !cs->singlestep_enabled) { + /* Direct jump. */ + tcg_gen_discard_i32(cpu_btarget); - if (unlikely(cs->singlestep_enabled)) { - gen_raise_exception(dc, EXCP_DEBUG); - } else { - tcg_gen_exit_tb(NULL, 0); - } - } - return; + if (dc->jmp_cond != TCG_COND_ALWAYS) { + /* Conditional direct jump. */ + TCGLabel *taken = gen_new_label(); + TCGv_i32 tmp = tcg_temp_new_i32(); - case JMP_DIRECT_CC: - { - TCGLabel *l1 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + /* + * Copy bvalue to a temp now, so we can discard bvalue. + * This can avoid writing bvalue to memory when the + * delay slot cannot raise an exception. + */ + tcg_gen_mov_i32(tmp, cpu_bvalue); + tcg_gen_discard_i32(cpu_bvalue); + + tcg_gen_brcondi_i32(dc->jmp_cond, tmp, 0, taken); gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); + gen_set_label(taken); } - /* fall through */ - - case JMP_DIRECT: - gen_goto_tb(dc, 0, dc->jmp_pc); + gen_goto_tb(dc, 0, dc->jmp_dest); return; } - /* fall through */ + + /* Indirect jump (or direct jump w/ singlestep) */ + tcg_gen_mov_i32(cpu_pc, cpu_btarget); + tcg_gen_discard_i32(cpu_btarget); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; default: g_assert_not_reached(); @@ -1867,8 +1830,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " BIMM"); } if (iflags & D_FLAG) { - qemu_fprintf(f, " D(btaken=%d btarget=0x%08x)", - env->btaken, env->btarget); + qemu_fprintf(f, " D(btarget=0x%08x)", env->btarget); } if (iflags & DRTI_FLAG) { qemu_fprintf(f, " DRTI"); @@ -1918,7 +1880,7 @@ void mb_tcg_init(void) SP(msr_c), SP(imm), SP(iflags), - SP(btaken), + SP(bvalue), SP(btarget), SP(res_val), };