diff mbox series

[v2,10/76] target/microblaze: Split out BTR from env->sregs

Message ID 20200828141929.77854-11-richard.henderson@linaro.org
State Superseded
Headers show
Series target/microblaze improvements | expand

Commit Message

Richard Henderson Aug. 28, 2020, 2:18 p.m. UTC 
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of BTR, yet.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/microblaze/cpu.h       | 1 +
 target/microblaze/gdbstub.c   | 4 ++--
 target/microblaze/helper.c    | 4 ++--
 target/microblaze/translate.c | 6 ++++--
 4 files changed, 9 insertions(+), 6 deletions(-)

-- 
2.25.1

Comments

Philippe Mathieu-Daudé Aug. 31, 2020, 8:53 p.m. UTC | #1 
Le ven. 28 août 2020 16:26, Richard Henderson <richard.henderson@linaro.org>
a écrit :

> Continue eliminating the sregs array in favor of individual members.

> Does not correct the width of BTR, yet.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


---
>  target/microblaze/cpu.h       | 1 +

>  target/microblaze/gdbstub.c   | 4 ++--

>  target/microblaze/helper.c    | 4 ++--

>  target/microblaze/translate.c | 6 ++++--

>  4 files changed, 9 insertions(+), 6 deletions(-)

>

> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h

> index bcafef99b0..deddb47abb 100644

> --- a/target/microblaze/cpu.h

> +++ b/target/microblaze/cpu.h

> @@ -241,6 +241,7 @@ struct CPUMBState {

>      uint64_t ear;

>      uint64_t esr;

>      uint64_t fsr;

> +    uint64_t btr;

>      uint64_t sregs[14];

>      float_status fp_status;

>      /* Stack protectors. Yes, it's a hw feature.  */

> diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c

> index 2634ce49fc..cde8c169bf 100644

> --- a/target/microblaze/gdbstub.c

> +++ b/target/microblaze/gdbstub.c

> @@ -74,7 +74,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray

> *mem_buf, int n)

>          val = env->fsr;

>          break;

>      case GDB_BTR:

> -        val = env->sregs[SR_BTR];

> +        val = env->btr;

>          break;

>      case GDB_PVR0 ... GDB_PVR11:

>          /* PVR12 is intentionally skipped */

> @@ -130,7 +130,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t

> *mem_buf, int n)

>          env->fsr = tmp;

>          break;

>      case GDB_BTR:

> -        env->sregs[SR_BTR] = tmp;

> +        env->btr = tmp;

>          break;

>      case GDB_PVR0 ... GDB_PVR11:

>          /* PVR12 is intentionally skipped */

> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c

> index ea290be780..b240dc76f6 100644

> --- a/target/microblaze/helper.c

> +++ b/target/microblaze/helper.c

> @@ -132,7 +132,7 @@ void mb_cpu_do_interrupt(CPUState *cs)

>              /* Exception breaks branch + dslot sequence?  */

>              if (env->iflags & D_FLAG) {

>                  env->esr |= 1 << 12 ;

> -                env->sregs[SR_BTR] = env->btarget;

> +                env->btr = env->btarget;

>              }

>

>              /* Disable the MMU.  */

> @@ -160,7 +160,7 @@ void mb_cpu_do_interrupt(CPUState *cs)

>              if (env->iflags & D_FLAG) {

>                  D(qemu_log("D_FLAG set at exception bimm=%d\n",

> env->bimm));

>                  env->esr |= 1 << 12 ;

> -                env->sregs[SR_BTR] = env->btarget;

> +                env->btr = env->btarget;

>

>                  /* Reexecute the branch.  */

>                  env->regs[17] -= 4;

> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c

> index c58c49ea8f..469e1f103a 100644

> --- a/target/microblaze/translate.c

> +++ b/target/microblaze/translate.c

> @@ -1811,7 +1811,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int

> flags)

>                   "rbtr=%" PRIx64 "\n",

>                   env->msr, env->esr, env->ear,

>                   env->debug, env->imm, env->iflags, env->fsr,

> -                 env->sregs[SR_BTR]);

> +                 env->btr);

>      qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "

>                   "eip=%d ie=%d\n",

>                   env->btaken, env->btarget,

> @@ -1879,8 +1879,10 @@ void mb_tcg_init(void)

>          tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr),

> "resr");

>      cpu_SR[SR_FSR] =

>          tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr),

> "rfsr");

> +    cpu_SR[SR_BTR] =

> +        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr),

> "rbtr");

>

> -    for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {

> +    for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) {

>          cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,

>                            offsetof(CPUMBState, sregs[i]),

>                            special_regnames[i]);

> --

> 2.25.1

>

>

>
<div dir="auto"><div><br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">Le ven. 28 août 2020 16:26, Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>&gt; a écrit :<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Continue eliminating the sregs array in favor of individual members.<br>
Does not correct the width of BTR, yet.<br>
<br>
Signed-off-by: Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org" target="_blank" rel="noreferrer">richard.henderson@linaro.org</a>&gt;<br></blockquote></div></div><div dir="auto"><br></div><div dir="auto"><span style="font-family:sans-serif;font-size:13.696px">Reviewed-by: Philippe Mathieu-Daudé &lt;</span><a href="mailto:f4bug@amsat.org" style="text-decoration:none;color:rgb(66,133,244);font-family:sans-serif;font-size:13.696px">f4bug@amsat.org</a><span style="font-family:sans-serif;font-size:13.696px">&gt;</span><br></div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">

---<br>
 target/microblaze/cpu.h       | 1 +<br>
 target/microblaze/gdbstub.c   | 4 ++--<br>
 target/microblaze/helper.c    | 4 ++--<br>
 target/microblaze/translate.c | 6 ++++--<br>
 4 files changed, 9 insertions(+), 6 deletions(-)<br>
<br>
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h<br>
index bcafef99b0..deddb47abb 100644<br>
--- a/target/microblaze/cpu.h<br>
+++ b/target/microblaze/cpu.h<br>
@@ -241,6 +241,7 @@ struct CPUMBState {<br>
     uint64_t ear;<br>
     uint64_t esr;<br>
     uint64_t fsr;<br>
+    uint64_t btr;<br>
     uint64_t sregs[14];<br>
     float_status fp_status;<br>
     /* Stack protectors. Yes, it&#39;s a hw feature.  */<br>
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c<br>
index 2634ce49fc..cde8c169bf 100644<br>
--- a/target/microblaze/gdbstub.c<br>
+++ b/target/microblaze/gdbstub.c<br>
@@ -74,7 +74,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)<br>
         val = env-&gt;fsr;<br>
         break;<br>
     case GDB_BTR:<br>
-        val = env-&gt;sregs[SR_BTR];<br>
+        val = env-&gt;btr;<br>
         break;<br>
     case GDB_PVR0 ... GDB_PVR11:<br>
         /* PVR12 is intentionally skipped */<br>
@@ -130,7 +130,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)<br>
         env-&gt;fsr = tmp;<br>
         break;<br>
     case GDB_BTR:<br>
-        env-&gt;sregs[SR_BTR] = tmp;<br>
+        env-&gt;btr = tmp;<br>
         break;<br>
     case GDB_PVR0 ... GDB_PVR11:<br>
         /* PVR12 is intentionally skipped */<br>
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c<br>
index ea290be780..b240dc76f6 100644<br>
--- a/target/microblaze/helper.c<br>
+++ b/target/microblaze/helper.c<br>
@@ -132,7 +132,7 @@ void mb_cpu_do_interrupt(CPUState *cs)<br>
             /* Exception breaks branch + dslot sequence?  */<br>
             if (env-&gt;iflags &amp; D_FLAG) {<br>
                 env-&gt;esr |= 1 &lt;&lt; 12 ;<br>
-                env-&gt;sregs[SR_BTR] = env-&gt;btarget;<br>
+                env-&gt;btr = env-&gt;btarget;<br>
             }<br>
<br>
             /* Disable the MMU.  */<br>
@@ -160,7 +160,7 @@ void mb_cpu_do_interrupt(CPUState *cs)<br>
             if (env-&gt;iflags &amp; D_FLAG) {<br>
                 D(qemu_log(&quot;D_FLAG set at exception bimm=%d\n&quot;, env-&gt;bimm));<br>
                 env-&gt;esr |= 1 &lt;&lt; 12 ;<br>
-                env-&gt;sregs[SR_BTR] = env-&gt;btarget;<br>
+                env-&gt;btr = env-&gt;btarget;<br>
<br>
                 /* Reexecute the branch.  */<br>
                 env-&gt;regs[17] -= 4;<br>
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c<br>
index c58c49ea8f..469e1f103a 100644<br>
--- a/target/microblaze/translate.c<br>
+++ b/target/microblaze/translate.c<br>
@@ -1811,7 +1811,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)<br>
                  &quot;rbtr=%&quot; PRIx64 &quot;\n&quot;,<br>
                  env-&gt;msr, env-&gt;esr, env-&gt;ear,<br>
                  env-&gt;debug, env-&gt;imm, env-&gt;iflags, env-&gt;fsr,<br>
-                 env-&gt;sregs[SR_BTR]);<br>
+                 env-&gt;btr);<br>
     qemu_fprintf(f, &quot;btaken=%d btarget=%&quot; PRIx64 &quot; mode=%s(saved=%s) &quot;<br>
                  &quot;eip=%d ie=%d\n&quot;,<br>
                  env-&gt;btaken, env-&gt;btarget,<br>
@@ -1879,8 +1879,10 @@ void mb_tcg_init(void)<br>
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), &quot;resr&quot;);<br>
     cpu_SR[SR_FSR] =<br>
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), &quot;rfsr&quot;);<br>
+    cpu_SR[SR_BTR] =<br>
+        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), &quot;rbtr&quot;);<br>
<br>
-    for (i = SR_FSR + 1; i &lt; ARRAY_SIZE(cpu_SR); i++) {<br>
+    for (i = SR_BTR + 1; i &lt; ARRAY_SIZE(cpu_SR); i++) {<br>
         cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,<br>
                           offsetof(CPUMBState, sregs[i]),<br>
                           special_regnames[i]);<br>
-- <br>
2.25.1<br>
<br>
<br>
</blockquote></div></div></div>
diff mbox series

Patch

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index bcafef99b0..deddb47abb 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -241,6 +241,7 @@  struct CPUMBState {
     uint64_t ear;
     uint64_t esr;
     uint64_t fsr;
+    uint64_t btr;
     uint64_t sregs[14];
     float_status fp_status;
     /* Stack protectors. Yes, it's a hw feature.  */
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 2634ce49fc..cde8c169bf 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -74,7 +74,7 @@  int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
         val = env->fsr;
         break;
     case GDB_BTR:
-        val = env->sregs[SR_BTR];
+        val = env->btr;
         break;
     case GDB_PVR0 ... GDB_PVR11:
         /* PVR12 is intentionally skipped */
@@ -130,7 +130,7 @@  int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
         env->fsr = tmp;
         break;
     case GDB_BTR:
-        env->sregs[SR_BTR] = tmp;
+        env->btr = tmp;
         break;
     case GDB_PVR0 ... GDB_PVR11:
         /* PVR12 is intentionally skipped */
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index ea290be780..b240dc76f6 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -132,7 +132,7 @@  void mb_cpu_do_interrupt(CPUState *cs)
             /* Exception breaks branch + dslot sequence?  */
             if (env->iflags & D_FLAG) {
                 env->esr |= 1 << 12 ;
-                env->sregs[SR_BTR] = env->btarget;
+                env->btr = env->btarget;
             }
 
             /* Disable the MMU.  */
@@ -160,7 +160,7 @@  void mb_cpu_do_interrupt(CPUState *cs)
             if (env->iflags & D_FLAG) {
                 D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
                 env->esr |= 1 << 12 ;
-                env->sregs[SR_BTR] = env->btarget;
+                env->btr = env->btarget;
 
                 /* Reexecute the branch.  */
                 env->regs[17] -= 4;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index c58c49ea8f..469e1f103a 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1811,7 +1811,7 @@  void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
                  "rbtr=%" PRIx64 "\n",
                  env->msr, env->esr, env->ear,
                  env->debug, env->imm, env->iflags, env->fsr,
-                 env->sregs[SR_BTR]);
+                 env->btr);
     qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
                  "eip=%d ie=%d\n",
                  env->btaken, env->btarget,
@@ -1879,8 +1879,10 @@  void mb_tcg_init(void)
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
     cpu_SR[SR_FSR] =
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
+    cpu_SR[SR_BTR] =
+        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr");
 
-    for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
+    for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
         cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
                           offsetof(CPUMBState, sregs[i]),
                           special_regnames[i]);