diff mbox series

[v2,09/76] target/microblaze: Split out FSR from env->sregs

Message ID 20200828141929.77854-10-richard.henderson@linaro.org
State Superseded
Headers show
Series target/microblaze improvements | expand

Commit Message

Richard Henderson Aug. 28, 2020, 2:18 p.m. UTC 
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of FSR, yet.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/microblaze/cpu.h          | 1 +
 linux-user/microblaze/cpu_loop.c | 4 ++--
 target/microblaze/gdbstub.c      | 4 ++--
 target/microblaze/op_helper.c    | 8 ++++----
 target/microblaze/translate.c    | 6 ++++--
 5 files changed, 13 insertions(+), 10 deletions(-)

-- 
2.25.1

Comments

Philippe Mathieu-Daudé Aug. 31, 2020, 8:51 p.m. UTC | #1 
Le ven. 28 août 2020 16:25, Richard Henderson <richard.henderson@linaro.org>
a écrit :

> Continue eliminating the sregs array in favor of individual members.

> Does not correct the width of FSR, yet.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


---
>  target/microblaze/cpu.h          | 1 +

>  linux-user/microblaze/cpu_loop.c | 4 ++--

>  target/microblaze/gdbstub.c      | 4 ++--

>  target/microblaze/op_helper.c    | 8 ++++----

>  target/microblaze/translate.c    | 6 ++++--

>  5 files changed, 13 insertions(+), 10 deletions(-)

>

> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h

> index 7d94af43ed..bcafef99b0 100644

> --- a/target/microblaze/cpu.h

> +++ b/target/microblaze/cpu.h

> @@ -240,6 +240,7 @@ struct CPUMBState {

>      uint64_t msr;

>      uint64_t ear;

>      uint64_t esr;

> +    uint64_t fsr;

>      uint64_t sregs[14];

>      float_status fp_status;

>      /* Stack protectors. Yes, it's a hw feature.  */

> diff --git a/linux-user/microblaze/cpu_loop.c

> b/linux-user/microblaze/cpu_loop.c

> index c10e3e0261..da5e98b784 100644

> --- a/linux-user/microblaze/cpu_loop.c

> +++ b/linux-user/microblaze/cpu_loop.c

> @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env)

>                  case ESR_EC_FPU:

>                      info.si_signo = TARGET_SIGFPE;

>                      info.si_errno = 0;

> -                    if (env->sregs[SR_FSR] & FSR_IO) {

> +                    if (env->fsr & FSR_IO) {

>                          info.si_code = TARGET_FPE_FLTINV;

>                      }

> -                    if (env->sregs[SR_FSR] & FSR_DZ) {

> +                    if (env->fsr & FSR_DZ) {

>                          info.si_code = TARGET_FPE_FLTDIV;

>                      }

>                      info._sifields._sigfault._addr = 0;

> diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c

> index 05e22f233d..2634ce49fc 100644

> --- a/target/microblaze/gdbstub.c

> +++ b/target/microblaze/gdbstub.c

> @@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray

> *mem_buf, int n)

>          val = env->esr;

>          break;

>      case GDB_FSR:

> -        val = env->sregs[SR_FSR];

> +        val = env->fsr;

>          break;

>      case GDB_BTR:

>          val = env->sregs[SR_BTR];

> @@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t

> *mem_buf, int n)

>          env->esr = tmp;

>          break;

>      case GDB_FSR:

> -        env->sregs[SR_FSR] = tmp;

> +        env->fsr = tmp;

>          break;

>      case GDB_BTR:

>          env->sregs[SR_BTR] = tmp;

> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c

> index f01cf9be64..ae57d45536 100644

> --- a/target/microblaze/op_helper.c

> +++ b/target/microblaze/op_helper.c

> @@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int

> flags)

>      int raise = 0;

>

>      if (flags & float_flag_invalid) {

> -        env->sregs[SR_FSR] |= FSR_IO;

> +        env->fsr |= FSR_IO;

>          raise = 1;

>      }

>      if (flags & float_flag_divbyzero) {

> -        env->sregs[SR_FSR] |= FSR_DZ;

> +        env->fsr |= FSR_DZ;

>          raise = 1;

>      }

>      if (flags & float_flag_overflow) {

> -        env->sregs[SR_FSR] |= FSR_OF;

> +        env->fsr |= FSR_OF;

>          raise = 1;

>      }

>      if (flags & float_flag_underflow) {

> -        env->sregs[SR_FSR] |= FSR_UF;

> +        env->fsr |= FSR_UF;

>          raise = 1;

>      }

>      if (raise

> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c

> index 411c7b6e49..c58c49ea8f 100644

> --- a/target/microblaze/translate.c

> +++ b/target/microblaze/translate.c

> @@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int

> flags)

>                   "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "

>                   "rbtr=%" PRIx64 "\n",

>                   env->msr, env->esr, env->ear,

> -                 env->debug, env->imm, env->iflags, env->sregs[SR_FSR],

> +                 env->debug, env->imm, env->iflags, env->fsr,

>                   env->sregs[SR_BTR]);

>      qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "

>                   "eip=%d ie=%d\n",

> @@ -1877,8 +1877,10 @@ void mb_tcg_init(void)

>          tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear),

> "rear");

>      cpu_SR[SR_ESR] =

>          tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr),

> "resr");

> +    cpu_SR[SR_FSR] =

> +        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr),

> "rfsr");

>

> -    for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) {

> +    for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {

>          cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,

>                            offsetof(CPUMBState, sregs[i]),

>                            special_regnames[i]);

> --

> 2.25.1

>

>

>
<div dir="auto"><div><br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">Le ven. 28 août 2020 16:25, Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>&gt; a écrit :<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Continue eliminating the sregs array in favor of individual members.<br>
Does not correct the width of FSR, yet.<br>
<br>
Signed-off-by: Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org" target="_blank" rel="noreferrer">richard.henderson@linaro.org</a>&gt;<br></blockquote></div></div><div dir="auto"><br></div><div dir="auto"><span style="font-family:sans-serif;font-size:13.696px">Reviewed-by: Philippe Mathieu-Daudé &lt;</span><a href="mailto:f4bug@amsat.org" style="text-decoration:none;color:rgb(66,133,244);font-family:sans-serif;font-size:13.696px">f4bug@amsat.org</a><span style="font-family:sans-serif;font-size:13.696px">&gt;</span><br></div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">

---<br>
 target/microblaze/cpu.h          | 1 +<br>
 linux-user/microblaze/cpu_loop.c | 4 ++--<br>
 target/microblaze/gdbstub.c      | 4 ++--<br>
 target/microblaze/op_helper.c    | 8 ++++----<br>
 target/microblaze/translate.c    | 6 ++++--<br>
 5 files changed, 13 insertions(+), 10 deletions(-)<br>
<br>
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h<br>
index 7d94af43ed..bcafef99b0 100644<br>
--- a/target/microblaze/cpu.h<br>
+++ b/target/microblaze/cpu.h<br>
@@ -240,6 +240,7 @@ struct CPUMBState {<br>
     uint64_t msr;<br>
     uint64_t ear;<br>
     uint64_t esr;<br>
+    uint64_t fsr;<br>
     uint64_t sregs[14];<br>
     float_status fp_status;<br>
     /* Stack protectors. Yes, it&#39;s a hw feature.  */<br>
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c<br>
index c10e3e0261..da5e98b784 100644<br>
--- a/linux-user/microblaze/cpu_loop.c<br>
+++ b/linux-user/microblaze/cpu_loop.c<br>
@@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env)<br>
                 case ESR_EC_FPU:<br>
                     info.si_signo = TARGET_SIGFPE;<br>
                     info.si_errno = 0;<br>
-                    if (env-&gt;sregs[SR_FSR] &amp; FSR_IO) {<br>
+                    if (env-&gt;fsr &amp; FSR_IO) {<br>
                         info.si_code = TARGET_FPE_FLTINV;<br>
                     }<br>
-                    if (env-&gt;sregs[SR_FSR] &amp; FSR_DZ) {<br>
+                    if (env-&gt;fsr &amp; FSR_DZ) {<br>
                         info.si_code = TARGET_FPE_FLTDIV;<br>
                     }<br>
                     info._sifields._sigfault._addr = 0;<br>
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c<br>
index 05e22f233d..2634ce49fc 100644<br>
--- a/target/microblaze/gdbstub.c<br>
+++ b/target/microblaze/gdbstub.c<br>
@@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)<br>
         val = env-&gt;esr;<br>
         break;<br>
     case GDB_FSR:<br>
-        val = env-&gt;sregs[SR_FSR];<br>
+        val = env-&gt;fsr;<br>
         break;<br>
     case GDB_BTR:<br>
         val = env-&gt;sregs[SR_BTR];<br>
@@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)<br>
         env-&gt;esr = tmp;<br>
         break;<br>
     case GDB_FSR:<br>
-        env-&gt;sregs[SR_FSR] = tmp;<br>
+        env-&gt;fsr = tmp;<br>
         break;<br>
     case GDB_BTR:<br>
         env-&gt;sregs[SR_BTR] = tmp;<br>
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c<br>
index f01cf9be64..ae57d45536 100644<br>
--- a/target/microblaze/op_helper.c<br>
+++ b/target/microblaze/op_helper.c<br>
@@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int flags)<br>
     int raise = 0;<br>
<br>
     if (flags &amp; float_flag_invalid) {<br>
-        env-&gt;sregs[SR_FSR] |= FSR_IO;<br>
+        env-&gt;fsr |= FSR_IO;<br>
         raise = 1;<br>
     }<br>
     if (flags &amp; float_flag_divbyzero) {<br>
-        env-&gt;sregs[SR_FSR] |= FSR_DZ;<br>
+        env-&gt;fsr |= FSR_DZ;<br>
         raise = 1;<br>
     }<br>
     if (flags &amp; float_flag_overflow) {<br>
-        env-&gt;sregs[SR_FSR] |= FSR_OF;<br>
+        env-&gt;fsr |= FSR_OF;<br>
         raise = 1;<br>
     }<br>
     if (flags &amp; float_flag_underflow) {<br>
-        env-&gt;sregs[SR_FSR] |= FSR_UF;<br>
+        env-&gt;fsr |= FSR_UF;<br>
         raise = 1;<br>
     }<br>
     if (raise<br>
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c<br>
index 411c7b6e49..c58c49ea8f 100644<br>
--- a/target/microblaze/translate.c<br>
+++ b/target/microblaze/translate.c<br>
@@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)<br>
                  &quot;debug=%x imm=%x iflags=%x fsr=%&quot; PRIx64 &quot; &quot;<br>
                  &quot;rbtr=%&quot; PRIx64 &quot;\n&quot;,<br>
                  env-&gt;msr, env-&gt;esr, env-&gt;ear,<br>
-                 env-&gt;debug, env-&gt;imm, env-&gt;iflags, env-&gt;sregs[SR_FSR],<br>
+                 env-&gt;debug, env-&gt;imm, env-&gt;iflags, env-&gt;fsr,<br>
                  env-&gt;sregs[SR_BTR]);<br>
     qemu_fprintf(f, &quot;btaken=%d btarget=%&quot; PRIx64 &quot; mode=%s(saved=%s) &quot;<br>
                  &quot;eip=%d ie=%d\n&quot;,<br>
@@ -1877,8 +1877,10 @@ void mb_tcg_init(void)<br>
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), &quot;rear&quot;);<br>
     cpu_SR[SR_ESR] =<br>
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), &quot;resr&quot;);<br>
+    cpu_SR[SR_FSR] =<br>
+        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), &quot;rfsr&quot;);<br>
<br>
-    for (i = SR_ESR + 1; i &lt; ARRAY_SIZE(cpu_SR); i++) {<br>
+    for (i = SR_FSR + 1; i &lt; ARRAY_SIZE(cpu_SR); i++) {<br>
         cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,<br>
                           offsetof(CPUMBState, sregs[i]),<br>
                           special_regnames[i]);<br>
-- <br>
2.25.1<br>
<br>
<br>
</blockquote></div></div></div>
diff mbox series

Patch

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 7d94af43ed..bcafef99b0 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -240,6 +240,7 @@  struct CPUMBState {
     uint64_t msr;
     uint64_t ear;
     uint64_t esr;
+    uint64_t fsr;
     uint64_t sregs[14];
     float_status fp_status;
     /* Stack protectors. Yes, it's a hw feature.  */
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
index c10e3e0261..da5e98b784 100644
--- a/linux-user/microblaze/cpu_loop.c
+++ b/linux-user/microblaze/cpu_loop.c
@@ -96,10 +96,10 @@  void cpu_loop(CPUMBState *env)
                 case ESR_EC_FPU:
                     info.si_signo = TARGET_SIGFPE;
                     info.si_errno = 0;
-                    if (env->sregs[SR_FSR] & FSR_IO) {
+                    if (env->fsr & FSR_IO) {
                         info.si_code = TARGET_FPE_FLTINV;
                     }
-                    if (env->sregs[SR_FSR] & FSR_DZ) {
+                    if (env->fsr & FSR_DZ) {
                         info.si_code = TARGET_FPE_FLTDIV;
                     }
                     info._sifields._sigfault._addr = 0;
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 05e22f233d..2634ce49fc 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -71,7 +71,7 @@  int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
         val = env->esr;
         break;
     case GDB_FSR:
-        val = env->sregs[SR_FSR];
+        val = env->fsr;
         break;
     case GDB_BTR:
         val = env->sregs[SR_BTR];
@@ -127,7 +127,7 @@  int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
         env->esr = tmp;
         break;
     case GDB_FSR:
-        env->sregs[SR_FSR] = tmp;
+        env->fsr = tmp;
         break;
     case GDB_BTR:
         env->sregs[SR_BTR] = tmp;
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index f01cf9be64..ae57d45536 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -175,19 +175,19 @@  static void update_fpu_flags(CPUMBState *env, int flags)
     int raise = 0;
 
     if (flags & float_flag_invalid) {
-        env->sregs[SR_FSR] |= FSR_IO;
+        env->fsr |= FSR_IO;
         raise = 1;
     }
     if (flags & float_flag_divbyzero) {
-        env->sregs[SR_FSR] |= FSR_DZ;
+        env->fsr |= FSR_DZ;
         raise = 1;
     }
     if (flags & float_flag_overflow) {
-        env->sregs[SR_FSR] |= FSR_OF;
+        env->fsr |= FSR_OF;
         raise = 1;
     }
     if (flags & float_flag_underflow) {
-        env->sregs[SR_FSR] |= FSR_UF;
+        env->fsr |= FSR_UF;
         raise = 1;
     }
     if (raise
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 411c7b6e49..c58c49ea8f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1810,7 +1810,7 @@  void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
                  "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
                  "rbtr=%" PRIx64 "\n",
                  env->msr, env->esr, env->ear,
-                 env->debug, env->imm, env->iflags, env->sregs[SR_FSR],
+                 env->debug, env->imm, env->iflags, env->fsr,
                  env->sregs[SR_BTR]);
     qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
                  "eip=%d ie=%d\n",
@@ -1877,8 +1877,10 @@  void mb_tcg_init(void)
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
     cpu_SR[SR_ESR] =
         tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
+    cpu_SR[SR_FSR] =
+        tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
 
-    for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
+    for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
         cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
                           offsetof(CPUMBState, sregs[i]),
                           special_regnames[i]);