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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 74/77] target/microblaze: Remove last of old decoder Date: Tue, 25 Aug 2020 13:59:47 -0700 Message-Id: <20200825205950.730499-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All instructions have been convered. Issue sigill if decodetree does not match. Remove argument decode from DisasContext. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 75 +---------------------------------- 1 file changed, 2 insertions(+), 73 deletions(-) -- 2.25.1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0a05b49f8e..2df22e8c2a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -65,13 +65,7 @@ typedef struct DisasContext { bool r0_set; /* Decoder. */ - int type_b; - uint32_t ir; uint32_t ext_imm; - uint8_t opcode; - uint8_t rd, ra, rb; - uint16_t imm; - unsigned int cpustate_changed; unsigned int tb_flags; unsigned int tb_flags_to_set; @@ -184,21 +178,6 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } -static int32_t dec_alu_typeb_imm(DisasContext *dc) -{ - tcg_debug_assert(dc->type_b); - return typeb_imm(dc, (int16_t)dc->imm); -} - -static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) -{ - if (dc->type_b) { - tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); - return &cpu_imm; - } - return &cpu_R[dc->rb]; -} - static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg != 0)) { @@ -1094,7 +1073,7 @@ static bool setup_dslot(DisasContext *dc) } dc->tb_flags_to_set |= D_FLAG; - if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + if (dc->tb_flags & IMM_FLAG) { dc->tb_flags_to_set |= BIMM_FLAG; } return false; @@ -1576,16 +1555,6 @@ static void do_rte(DisasContext *dc) dc->tb_flags &= ~DRTE_FLAG; } -static void dec_null(DisasContext *dc) -{ - if (trap_illegal(dc, true)) { - return; - } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", - (uint32_t)dc->base.pc_next, dc->opcode); - dc->abort_at_next_insn = 1; -} - /* Insns connected to FSL or AXI stream attached devices. */ static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { @@ -1651,46 +1620,6 @@ static bool trans_putd(DisasContext *dc, arg_putd *arg) return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } -static struct decoder_info { - struct { - uint32_t bits; - uint32_t mask; - }; - void (*dec)(DisasContext *dc); -} decinfo[] = { - {{0, 0}, dec_null} -}; - -static void old_decode(DisasContext *dc, uint32_t ir) -{ - int i; - - dc->ir = ir; - - if (ir == 0) { - trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); - /* Don't decode nop/zero instructions any further. */ - return; - } - - /* bit 2 seems to indicate insn type. */ - dc->type_b = ir & (1 << 29); - - dc->opcode = EXTRACT_FIELD(ir, 26, 31); - dc->rd = EXTRACT_FIELD(ir, 21, 25); - dc->ra = EXTRACT_FIELD(ir, 16, 20); - dc->rb = EXTRACT_FIELD(ir, 11, 15); - dc->imm = EXTRACT_FIELD(ir, 0, 15); - - /* Large switch for all insns. */ - for (i = 0; i < ARRAY_SIZE(decinfo); i++) { - if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { - decinfo[i].dec(dc); - break; - } - } -} - static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); @@ -1757,7 +1686,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) ir = cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { - old_decode(dc, ir); + trap_illegal(dc, true); } if (dc->r0) {