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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 71/77] target/microblaze: Convert msrclr, msrset to decodetree Date: Tue, 25 Aug 2020 13:59:44 -0700 Message-Id: <20200825205950.730499-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this out of dec_msr. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 85 +++++++++++++++++++--------------- 2 files changed, 54 insertions(+), 37 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index f12e85b492..e80283cce6 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -24,6 +24,7 @@ &typeb rd ra imm &typeb_br rd imm &typeb_bc ra imm +&type_msr rd imm # Include any IMM prefix in the value reported. %extimm 0:s16 !function=typeb_imm @@ -55,6 +56,8 @@ %ieimm 6:5 0:5 @typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm +@type_msr ...... rd:5 ...... imm:15 &type_msr + ### add 000000 ..... ..... ..... 000 0000 0000 @typea @@ -176,6 +179,9 @@ lwi 111010 ..... ..... ................ @typeb mbar 101110 imm:5 00010 0000 0000 0000 0100 +msrclr 100101 ..... 100010 ............... @type_msr +msrset 100101 ..... 100000 ............... @type_msr + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 71ceabfffd..e05523bd5b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1338,16 +1338,61 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } +static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) +{ + uint32_t imm = arg->imm; + + if (trap_userspace(dc, imm != MSR_C)) { + return true; + } + + if (arg->rd) { + msr_read(dc, cpu_R[arg->rd]); + } + + /* + * Handle the carry bit separately. + * This is the only bit that userspace can modify. + */ + if (imm & MSR_C) { + tcg_gen_movi_i32(cpu_msr_c, set); + } + + /* + * MSR_C and MSR_CC set above. + * MSR_PVR is not writable, and is always clear. + */ + imm &= ~(MSR_C | MSR_CC | MSR_PVR); + + if (imm != 0) { + if (set) { + tcg_gen_ori_i32(cpu_msr, cpu_msr, imm); + } else { + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); + } + dc->cpustate_changed = 1; + } + return true; +} + +static bool trans_msrclr(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, false); +} + +static bool trans_msrset(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, true); +} + static void dec_msr(DisasContext *dc) { CPUState *cs = CPU(dc->cpu); - TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset, extended = false; + bool to, extended = false; sr = extract32(dc->imm, 0, 14); to = extract32(dc->imm, 14, 1); - clrset = extract32(dc->imm, 15, 1) == 0; dc->type_b = 1; if (to) { dc->cpustate_changed = 1; @@ -1361,40 +1406,6 @@ static void dec_msr(DisasContext *dc) extended = extract32(dc->imm, e_bit[to], 1); } - /* msrclr and msrset. */ - if (clrset) { - bool clr = extract32(dc->ir, 16, 1); - - if (!dc->cpu->cfg.use_msr_instr) { - /* nop??? */ - return; - } - - if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) { - return; - } - - if (dc->rd) - msr_read(dc, cpu_R[dc->rd]); - - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - msr_read(dc, t0); - tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); - - if (clr) { - tcg_gen_not_i32(t1, t1); - tcg_gen_and_i32(t0, t0, t1); - } else - tcg_gen_or_i32(t0, t0, t1); - msr_write(dc, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - dc->base.is_jmp = DISAS_UPDATE; - return; - } - if (trap_userspace(dc, to)) { return; }