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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 67/77] target/microblaze: Convert dec_br to decodetree Date: Tue, 25 Aug 2020 13:59:40 -0700 Message-Id: <20200825205950.730499-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 14 +++++ target/microblaze/translate.c | 98 +++++++++++++++++++--------------- 2 files changed, 68 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 77b073be9e..94520e92dd 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -65,6 +65,20 @@ andi 101001 ..... ..... ................ @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb +br 100110 ..... 00000 ..... 000 0000 0000 @typea_br +bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br +brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br +brad 100110 ..... 11000 ..... 000 0000 0000 @typea_br +brld 100110 ..... 10100 ..... 000 0000 0000 @typea_br +brald 100110 ..... 11100 ..... 000 0000 0000 @typea_br + +bri 101110 ..... 00000 ................ @typeb_br +brai 101110 ..... 01000 ................ @typeb_br +brid 101110 ..... 10000 ................ @typeb_br +braid 101110 ..... 11000 ................ @typeb_br +brlid 101110 ..... 10100 ................ @typeb_br +bralid 101110 ..... 11100 ................ @typeb_br + brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br brki 101110 ..... 01100 ................ @typeb_br diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 5bd771671b..73c956cd76 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1087,6 +1087,58 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) return true; } +static bool setup_dslot(DisasContext *dc) +{ + if (wait_for_next_tb(dc)) { + return true; + } + + dc->tb_flags_to_set |= D_FLAG; + if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags_to_set |= BIMM_FLAG; + } + return false; +} + +static bool do_branch(DisasContext *dc, int dest_rb, int dest_imm, + bool delay, bool abs, int link) +{ + uint32_t add_pc; + + if (delay && setup_dslot(dc)) { + return true; + } + + if (link) { + tcg_gen_movi_i32(cpu_R[link], dc->base.pc_next); + } + + /* Store the branch taken destination into btarget. */ + add_pc = abs ? 0 : dc->base.pc_next; + if (dest_rb) { + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], add_pc); + } else { + dc->jmp_dest = add_pc + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + dc->jmp_cond = TCG_COND_ALWAYS; + return true; +} + +#define DO_BR(NAME, NAMEI, DELAY, ABS, LINK) \ + static bool trans_##NAME(DisasContext *dc, arg_typea_br *arg) \ + { return do_branch(dc, arg->rb, 0, DELAY, ABS, LINK ? arg->rd : 0); } \ + static bool trans_##NAMEI(DisasContext *dc, arg_typeb_br *arg) \ + { return do_branch(dc, 0, arg->imm, DELAY, ABS, LINK ? arg->rd : 0); } + +DO_BR(br, bri, false, false, false) +DO_BR(bra, brai, false, true, false) +DO_BR(brd, brid, true, false, false) +DO_BR(brad, braid, true, true, false) +DO_BR(brld, brlid, true, false, true) +DO_BR(brald, bralid, true, true, true) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1393,19 +1445,6 @@ static void dec_msr(DisasContext *dc) } } -static bool dec_setup_dslot(DisasContext *dc) -{ - if (wait_for_next_tb(dc)) { - return true; - } - - dc->tb_flags_to_set |= D_FLAG; - if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags_to_set |= BIMM_FLAG; - } - return false; -} - static void dec_bcc(DisasContext *dc) { static const TCGCond mb_to_tcg_cc[] = { @@ -1423,7 +1462,7 @@ static void dec_bcc(DisasContext *dc) cc = EXTRACT_FIELD(dc->ir, 21, 23); dslot = dc->ir & (1 << 25); - if (dslot && dec_setup_dslot(dc)) { + if (dslot && setup_dslot(dc)) { return; } @@ -1452,34 +1491,6 @@ static void dec_bcc(DisasContext *dc) tcg_temp_free_i32(next); } -static void dec_br(DisasContext *dc) -{ - unsigned int dslot, link, abs; - uint32_t add_pc; - - dslot = dc->ir & (1 << 20); - abs = dc->ir & (1 << 19); - link = dc->ir & (1 << 18); - - if (dslot && dec_setup_dslot(dc)) { - return; - } - - if (link && dc->rd) { - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - } - - add_pc = abs ? 0 : dc->base.pc_next; - if (dc->type_b) { - dc->jmp_dest = add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest = -1; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); - } - dc->jmp_cond = TCG_COND_ALWAYS; -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1548,7 +1559,7 @@ static void dec_rts(DisasContext *dc) return; } - if (dec_setup_dslot(dc)) { + if (setup_dslot(dc)) { return; } @@ -1612,7 +1623,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr},