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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 38/77] target/microblaze: Implement cmp and cmpu inline Date: Tue, 25 Aug 2020 13:59:11 -0700 Message-Id: <20200825205950.730499-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are simple enough operations; we do not need to call an out-of-line helper. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 -- target/microblaze/op_helper.c | 20 -------------------- target/microblaze/translate.c | 24 ++++++++++++++++++++++-- 3 files changed, 22 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 988abf7661..6f7f96421f 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,6 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_2(cmp, i32, i32, i32) -DEF_HELPER_2(cmpu, i32, i32, i32) DEF_HELPER_3(divs, i32, env, i32, i32) DEF_HELPER_3(divu, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 9bb6a2ad76..f976d112eb 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t index) cpu_loop_exit(cs); } -uint32_t helper_cmp(uint32_t a, uint32_t b) -{ - uint32_t t; - - t = b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t = (t & 0x7fffffff) | (b & 0x80000000); - return t; -} - -uint32_t helper_cmpu(uint32_t a, uint32_t b) -{ - uint32_t t; - - t = b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t = (t & 0x7fffffff) | (a & 0x80000000); - return t; -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu = env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 98050f64b7..ce91645f05 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,8 +327,28 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) -DO_TYPEA(cmp, false, gen_helper_cmp) -DO_TYPEA(cmpu, false, gen_helper_cmpu) +static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt = tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt = tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +DO_TYPEA(cmp, false, gen_cmp) +DO_TYPEA(cmpu, false, gen_cmpu) /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)