From patchwork Tue Aug 25 20:59:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 248277 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp3770332ils; Tue, 25 Aug 2020 14:09:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz88iQqHIeOOcnd4m0fq3Vw1xgocNRdxZ4738yEpZsQIeMrYyhpfKaXHGYA0HVg6QT1aJmz X-Received: by 2002:a25:e00e:: with SMTP id x14mr16914099ybg.263.1598389774580; Tue, 25 Aug 2020 14:09:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598389774; cv=none; d=google.com; s=arc-20160816; b=PY0tFjnawAY2aKlVJiLO0MaTmwT46uKsUIL3Ilxn31MgTohW6nbfYlWyTfJfL9T1hm kblOM0oJbHPpp5GGA8zCvJfasGLAqOgOiCIT6wBDZF9zpxSpCstfGHogKC/aq/pJo+1Y I7ryTIIQX5Fz6QQbPOKaLsWuB0hQ3psi7RHsm+V4/5mlT0+CWd3cX43WhfFwHXGU61+X quQExybq7MP6f9JDVupqT55Pg4cvHn6nUkFBvsZsSK4TopH2NNnlMUixo0XzwxPKEDAN aEWO73KFdpqUpkWuymUMciZz/cuOjgmijicrbgVmszmfy+L0Ubd3MQr18FQKf6xRgIoH hW0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3tIkPYiOnQsOVuosyAmz/ThXo6OaMIkZVJ4NrFAYJ24=; b=XhuFqGaKhHjFHg9WbOGgPQts34xubT9YfloJV3VNmn9HbqSBwtTSOsmGMFMF6M7vf1 AF7//JcVx4ABRKLTmlqxVh6UCIDwAv7MBHMNxrGe8vahgJajkRe0ARwisch0PmVbcTfT 2sBhoVKGz0zZPQ0MbK5qghIty3e9PB2eKlzRNWZDO4Hjvlsr/ElaOyLK+U9Kjl4tLV5l YR6jZIsT+3IDEDoynIYQ8dtUeshYuTs8ZOAE3rwaOR+Iu7/fX0++/IUtAIBY9GdLyPVs Sj+YGCXeL/PdQrytkJBVRQdA+IuQ+og2eHud5ElIJbW6SRzaijF4srJclJvNeZ7mun8T CrKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d1Qixezz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k8si24536ybt.344.2020.08.25.14.09.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Aug 2020 14:09:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d1Qixezz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgCE-0004Ss-18 for patch@linaro.org; Tue, 25 Aug 2020 17:09:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3f-0007z1-32 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:43 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:40609) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3c-0001r0-Gg for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:42 -0400 Received: by mail-pf1-x434.google.com with SMTP id k18so8290128pfp.7 for ; Tue, 25 Aug 2020 14:00:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3tIkPYiOnQsOVuosyAmz/ThXo6OaMIkZVJ4NrFAYJ24=; b=d1Qixezz4UmtbVqg6O8QBMEyxiyEOcwRzNwhQmDTZru/tTC3iTy/ZQd7z+05TTxHHQ O42RZO1StDXEmUk4kanYFg3e7IQNpf8U5rf8YDbX2GTFF0ybOnx8gwgFz3cCQw8Cpzvj v7IuDMN6cDHQ1MqV7HpVlnpPhlW1/BROmoplSq+2d9QBEeaU33ac0JvSRFFLHMAlTtIm J335t16aWorSOYiZjAX6zMENsXSVx+F98wYwZUxeDiECD5yHFxKzQsWEbCMtnjC0KQyd sR2bQ2GFa8TP/fMR4VxHiYP3aHcjxyYyTMdt28A5v4ccSKF0m1+Nq33opiEyk4yJ2kBQ HKYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3tIkPYiOnQsOVuosyAmz/ThXo6OaMIkZVJ4NrFAYJ24=; b=Gvn+eRK7nxZhZZjKRrKv/fDAf3pX9Xv60HsrRbjlUCpIPS3Yg3PgHzaUht4lzLjtcN c46YT+O0IOpwa4dGY2gpOkU1tIY9iHQW4Gk+8B8Y48uw7wdXKTbiOrNQUQSbdtBvSrk7 +dEVdm4wuzQI70RNi1z4qvx7+vH6jEzTFMOWjFfTqNZG/xrdffMAE5GeiVP+vp6V0mrQ BpZmJ8XBzOq/X9Jsm5PvToeWt2QZSZ4+NNfMn721a94OoaYXxYZOmuC3l96XxYI2Hahd xAjdYXKU9jEDLj2Xuy/fxzLVAt7ka2+TGnHwI/IR8xUY8OB0oPzlcrTSmAFCdzqxmU8s asww== X-Gm-Message-State: AOAM533PGwr33mXsoP2WJ2jAQFKxqcmqPXWnEAxOKRIZ6u3sHAw5QY/h VIkH4OHYD78/ux71YLtLCpbM9Blg/BY/vw== X-Received: by 2002:a62:9256:: with SMTP id o83mr9051189pfd.44.1598389238266; Tue, 25 Aug 2020 14:00:38 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 36/77] target/microblaze: Convert dec_add to decodetree Date: Tue, 25 Aug 2020 13:59:09 -0700 Message-Id: <20200825205950.730499-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Adds infrastrucure for translation of instructions, which could not be added before their first use. Cache a temporary which represents r0 as the immediate 0 value, or a sink. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 21 ++++ target/microblaze/translate.c | 185 +++++++++++++++++++++++++-------- 2 files changed, 165 insertions(+), 41 deletions(-) -- 2.25.1 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 1ed9ca0731..c62f826bcc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -16,3 +16,24 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +&typea rd ra rb +&typeb rd ra imm + +# Include any IMM prefix in the value reported. +%extimm 0:s16 !function=typeb_imm + +@typea ...... rd:5 ra:5 rb:5 ... .... .... &typea +@typeb ...... rd:5 ra:5 ................ &typeb imm=%extimm + +### + +add 000000 ..... ..... ..... 000 0000 0000 @typea +addc 000010 ..... ..... ..... 000 0000 0000 @typea +addk 000100 ..... ..... ..... 000 0000 0000 @typea +addkc 000110 ..... ..... ..... 000 0000 0000 @typea + +addi 001000 ..... ..... ................ @typeb +addic 001010 ..... ..... ................ @typeb +addik 001100 ..... ..... ................ @typeb +addikc 001110 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e624093745..c3cc4db629 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; + TCGv_i32 r0; + bool r0_set; + /* Decoder. */ int type_b; uint32_t ir; @@ -81,6 +84,14 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; +static int typeb_imm(DisasContext *dc, int x) +{ + if (dc->tb_flags & IMM_FLAG) { + return deposit32(dc->ext_imm, 0, 16, x); + } + return x; +} + /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -176,11 +187,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) static int32_t dec_alu_typeb_imm(DisasContext *dc) { tcg_debug_assert(dc->type_b); - if (dc->tb_flags & IMM_FLAG) { - return dc->ext_imm | dc->imm; - } else { - return (int16_t)dc->imm; - } + return typeb_imm(dc, (int16_t)dc->imm); } static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) @@ -192,46 +199,134 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) return &cpu_R[dc->rb]; } -static void dec_add(DisasContext *dc) +static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { - unsigned int k, c; - TCGv_i32 cf; - - k = dc->opcode & 4; - c = dc->opcode & 2; - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd == r0, it's a nop. */ - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } + if (likely(reg != 0)) { + return cpu_R[reg]; + } + if (!dc->r0_set) { + if (dc->r0 == NULL) { + dc->r0 = tcg_temp_new_i32(); } - return; + tcg_gen_movi_i32(dc->r0, 0); + dc->r0_set = true; } - - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. */ - cf = tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 0); - } - - gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - } - tcg_temp_free_i32(cf); + return dc->r0; } +static TCGv_i32 reg_for_write(DisasContext *dc, int reg) +{ + if (likely(reg != 0)) { + return cpu_R[reg]; + } + if (dc->r0 == NULL) { + dc->r0 = tcg_temp_new_i32(); + } + return dc->r0; +} + +static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, rb; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + rb = reg_for_read(dc, arg->rb); + fn(rd, ra, rb); + return true; +} + +static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects, + void (*fni)(TCGv_i32, TCGv_i32, int32_t)) +{ + TCGv_i32 rd, ra; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + fni(rd, ra, arg->imm); + return true; +} + +static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, imm; + + if (arg->rd == 0 && !side_effects) { + return true; + } + + rd = reg_for_write(dc, arg->rd); + ra = reg_for_read(dc, arg->ra); + imm = tcg_const_i32(arg->imm); + + fn(rd, ra, imm); + + tcg_temp_free_i32(imm); + return true; +} + +#define DO_TYPEA(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return do_typea(dc, a, SE, FN); } + +#define DO_TYPEBI(NAME, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_imm(dc, a, SE, FNI); } + +#define DO_TYPEBV(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_val(dc, a, SE, FN); } + +/* No input carry, but output carry. */ +static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + + tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero); + + tcg_temp_free_i32(zero); +} + +/* Input and output carry. */ +static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(zero); +} + +/* Input carry, but no output carry. */ +static void gen_addkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_add_i32(out, ina, inb); + tcg_gen_add_i32(out, out, cpu_msr_c); +} + +DO_TYPEA(add, true, gen_add) +DO_TYPEA(addc, true, gen_addc) +DO_TYPEA(addk, false, tcg_gen_add_i32) +DO_TYPEA(addkc, true, gen_addkc) + +DO_TYPEBV(addi, true, gen_add) +DO_TYPEBV(addic, true, gen_addc) +DO_TYPEBI(addik, false, tcg_gen_addi_i32) +DO_TYPEBV(addikc, true, gen_addkc) + static void dec_sub(DisasContext *dc) { unsigned int u, cmp, k, c; @@ -1488,7 +1583,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_ADD, dec_add}, {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, @@ -1552,6 +1646,8 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->ext_imm = dc->base.tb->cs_base; + dc->r0 = NULL; + dc->r0_set = false; bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); @@ -1600,6 +1696,13 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) if (!decode(dc, ir)) { old_decode(dc, ir); } + + if (dc->r0) { + tcg_temp_free_i32(dc->r0); + dc->r0 = NULL; + dc->r0_set = false; + } + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &= ~IMM_FLAG; tcg_gen_discard_i32(cpu_imm);