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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/77] target/microblaze: Fix width of BTR Date: Tue, 25 Aug 2020 13:58:50 -0700 Message-Id: <20200825205950.730499-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The branch target register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_btr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 12 +++++------- 2 files changed, 6 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 34177f9b28..72f068a5fd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,7 +241,7 @@ struct CPUMBState { uint64_t ear; uint32_t esr; uint32_t fsr; - uint64_t btr; + uint32_t btr; uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3fc2feda3d..a2bba0fe61 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -545,7 +544,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); @@ -587,7 +587,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); @@ -1799,8 +1800,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " - "debug=%x imm=%x iflags=%x fsr=%x " - "rbtr=%" PRIx64 "\n", + "debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); @@ -1868,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_btr = - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); }