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d="scan'208";a="144994825" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 14 Aug 2020 23:15:13 +0800 IronPort-SDR: zQxYHQNvIyoEVRyAbu/pS/y4hC+zmFgQrpfXFZj5u0ejoCE1y6TIs5mMz6rhp31eAJysoEpY9k u9AOYvtK20Xg== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2020 08:02:17 -0700 IronPort-SDR: eeVj4A8pBahRF/3LPWNFo0dlodAciz4IVnJ9fiR1pOR+vFQdjpG/p7cC1DoRffYX+CShVaEhUx ntgfFbNZngFA== WDCIronportException: Internal Received: from jbfyk72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.14]) by uls-op-cesaip02.wdc.com with ESMTP; 14 Aug 2020 08:15:12 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v2 07/20] target/riscv: check before allocating TCG temps Date: Fri, 14 Aug 2020 08:04:53 -0700 Message-Id: <20200814150506.2070566-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814150506.2070566-1-alistair.francis@wdc.com> References: <20200814150506.2070566-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=4887bfbec=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/14 11:15:11 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Richard Henderson , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Richard Henderson Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson Message-Id: <20200724002807.441147-8-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++---- target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c index ea1044f13b..4f832637fa 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -20,10 +20,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); @@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 138e317723..3dfec8211d 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -25,10 +25,10 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); @@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);