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[209.51.188.17]) by mx.google.com with ESMTPS id 7si6200569yba.196.2020.08.13.13.04.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Aug 2020 13:04:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oeVRJvRs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6JSu-00019R-Ay for patch@linaro.org; Thu, 13 Aug 2020 16:04:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6JR8-00074I-UG for qemu-devel@nongnu.org; Thu, 13 Aug 2020 16:02:54 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:44272) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6JR5-0002ux-Nn for qemu-devel@nongnu.org; Thu, 13 Aug 2020 16:02:54 -0400 Received: by mail-pf1-x42d.google.com with SMTP id r11so3350670pfl.11 for ; Thu, 13 Aug 2020 13:02:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CgDBPf2Dk1ElYOV7ehDG3RN8j+NrQaxsKiOU3MkvFnI=; b=oeVRJvRsjeWRjyr1e5zCSid339RZzTEBuNBeTZxHAx1KUiAvCvhzt72dGx55qjPieo xQyNK01aWK5Ae66JoIrqPJBMBmIsPLr7MVQ4auKf3bKtqJ/sLyUM/cKv5sy/q+LaXOMP plBmgoK3btCP58xnbqvVoTzLtFHT045UARD0hxvKx7208QML9CXn/vChkd7XAeABC+cB p6lAFniLr9Y7QvI+6Wg+LzGIL/BDxTJ8dduniTtS+5INKOXPqgSvaMeqr5onKd7BKGWS 2QtzGWifc1Jzd1ZafD/qCmBxl22oDNsY4q3kxiqfjECnlSdVsC1W3nI/0OWDkROnccgA sQ1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CgDBPf2Dk1ElYOV7ehDG3RN8j+NrQaxsKiOU3MkvFnI=; b=ieczIYc09T/kjxjGmde+4Wi7f45mfofOg9J+TVyObMoLJU2taygNmrhe3buzMtbqO3 CrQ2M3A4L1T98ZMv+qiBM3Et3fxfoKyxfXzSskfi9A4uQRBo3m9ig0fGsYrkudKmgrDy UMmR7SdkoxBvSK+LRqz0ZxUmyGol+zAl92dUZHCPX1Eifa6yTSKhgYGxCs11cnKk4dP9 MyrL26hkgm/ts9yzb9pnbCz/2qeMhXQdGzuq3vbgpfNuN2R2nUKQQiAHSFfSAQcgtxyG 0I7Kk+qIW2vYVUZwphtfnjHqI+czvUyVQJfbOaH1yvXTs2Bzn48uQR6mglJak+1R122U D7rw== X-Gm-Message-State: AOAM531Yyf6LSWXJfOXPf+2K8kYbLsu6MmEX4zY2LXVU23hr3UDfPl91 v/2cbJftpouhCwqMHtalAXH+0etCLDE= X-Received: by 2002:aa7:9241:: with SMTP id 1mr6201677pfp.188.1597348968269; Thu, 13 Aug 2020 13:02:48 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id h12sm6871103pfr.143.2020.08.13.13.02.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 13:02:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 2/3] target/arm: Implement an IMPDEF pauth algorithm Date: Thu, 13 Aug 2020 13:02:42 -0700 Message-Id: <20200813200243.3036772-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200813200243.3036772-1-richard.henderson@linaro.org> References: <20200813200243.3036772-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, peter.maydell@linaro.org, drjones@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Without hardware acceleration, a cryptographically strong algorithm is too expensive for pauth_computepac. Even with hardware accel, we are not currently expecting to link the linux-user binaries to any crypto libraries, and doing so would generally make the --static build fail. So choose XXH64 as a reasonably quick and decent hash. Signed-off-by: Richard Henderson --- v2: Move the XXH64 bits to xxhash.h (ajb). Create isar_feature_aa64_pauth_arch and fixup a comment in isar_feature_aa64_pauth that no longer applies. --- include/qemu/xxhash.h | 82 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 15 +++++-- target/arm/pauth_helper.c | 41 +++++++++++++++++--- 3 files changed, 129 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/include/qemu/xxhash.h b/include/qemu/xxhash.h index 076f1f6054..93ba1a0425 100644 --- a/include/qemu/xxhash.h +++ b/include/qemu/xxhash.h @@ -119,4 +119,86 @@ static inline uint32_t qemu_xxhash6(uint64_t ab, uint64_t cd, uint32_t e, return qemu_xxhash7(ab, cd, e, f, 0); } +/* + * Component parts of the XXH64 algorithm from + * https://github.com/Cyan4973/xxHash/blob/v0.8.0/xxhash.h + * + * The complete algorithm looks like + * + * i = 0; + * if (len >= 32) { + * v1 = seed + PRIME64_1 + PRIME64_2; + * v2 = seed + PRIME64_2; + * v3 = seed + 0; + * v4 = seed - XXH_PRIME64_1; + * do { + * v1 = XXH64_round(v1, get64bits(input + i)); + * v2 = XXH64_round(v2, get64bits(input + i + 8)); + * v3 = XXH64_round(v3, get64bits(input + i + 16)); + * v4 = XXH64_round(v4, get64bits(input + i + 24)); + * } while ((i += 32) <= len); + * h64 = XXH64_mergerounds(v1, v2, v3, v4); + * } else { + * h64 = seed + PRIME64_5; + * } + * h64 += len; + * + * for (; i + 8 <= len; i += 8) { + * h64 ^= XXH64_round(0, get64bits(input + i)); + * h64 = rol64(h64, 27) * PRIME64_1 + PRIME64_4; + * } + * for (; i + 4 <= len; i += 4) { + * h64 ^= get32bits(input + i) * PRIME64_1; + * h64 = rol64(h64, 23) * PRIME64_2 + PRIME64_3; + * } + * for (; i < len; i += 1) { + * h64 ^= get8bits(input + i) * PRIME64_5; + * h64 = rol64(h64, 11) * PRIME64_1; + * } + * + * return XXH64_avalanche(h64) + * + * Exposing the pieces instead allows for simplified usage when + * the length is a known constant and the inputs are in registers. + */ +#define PRIME64_1 0x9E3779B185EBCA87ULL +#define PRIME64_2 0xC2B2AE3D27D4EB4FULL +#define PRIME64_3 0x165667B19E3779F9ULL +#define PRIME64_4 0x85EBCA77C2B2AE63ULL +#define PRIME64_5 0x27D4EB2F165667C5ULL + +static inline uint64_t XXH64_round(uint64_t acc, uint64_t input) +{ + return rol64(acc + input * PRIME64_2, 31) * PRIME64_1; +} + +static inline uint64_t XXH64_mergeround(uint64_t acc, uint64_t val) +{ + return (acc ^ XXH64_round(0, val)) * PRIME64_1 + PRIME64_4; +} + +static inline uint64_t XXH64_mergerounds(uint64_t v1, uint64_t v2, + uint64_t v3, uint64_t v4) +{ + uint64_t h64; + + h64 = rol64(v1, 1) + rol64(v2, 7) + rol64(v3, 12) + rol64(v4, 18); + h64 = XXH64_mergeround(h64, v1); + h64 = XXH64_mergeround(h64, v2); + h64 = XXH64_mergeround(h64, v3); + h64 = XXH64_mergeround(h64, v4); + + return h64; +} + +static inline uint64_t XXH64_avalanche(uint64_t h64) +{ + h64 ^= h64 >> 33; + h64 *= PRIME64_2; + h64 ^= h64 >> 29; + h64 *= PRIME64_3; + h64 ^= h64 >> 32; + return h64; +} + #endif /* QEMU_XXHASH_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 44901923c8..776bf30cbc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3767,10 +3767,8 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) { /* - * Note that while QEMU will only implement the architected algorithm - * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation - * defined algorithms, and thus API+GPI, and this predicate controls - * migration of the 128-bit keys. + * Return true if any form of pauth is enabled, as this + * predicate controls migration of the 128-bit keys. */ return (id->id_aa64isar1 & (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | @@ -3779,6 +3777,15 @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; } +static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) +{ + /* + * Return true if pauth is enabled with the architected QARMA algorithm. + * QEMU will always set APA+GPA to the same value. + */ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 6dbab03768..6ec4f83ff0 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -24,6 +24,7 @@ #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" +#include "qemu/xxhash.h" static uint64_t pac_cell_shuffle(uint64_t i) @@ -207,8 +208,8 @@ static uint64_t tweak_inv_shuffle(uint64_t i) return o; } -static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, - ARMPACKey key) +static uint64_t __attribute__((noinline)) +pauth_computepac_architected(uint64_t data, uint64_t modifier, ARMPACKey key) { static const uint64_t RC[5] = { 0x0000000000000000ull, @@ -272,6 +273,36 @@ static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, return workingval; } +/* + * The XXH64 algorithm from + * https://github.com/Cyan4973/xxHash/blob/v0.8.0/xxhash.h + */ +static uint64_t __attribute__((noinline)) +pauth_computepac_impdef(uint64_t data, uint64_t modifier, ARMPACKey key) +{ + uint64_t v1 = QEMU_XXHASH_SEED + PRIME64_1 + PRIME64_2; + uint64_t v2 = QEMU_XXHASH_SEED + PRIME64_2; + uint64_t v3 = QEMU_XXHASH_SEED + 0; + uint64_t v4 = QEMU_XXHASH_SEED - PRIME64_1; + + v1 = XXH64_round(v1, data); + v2 = XXH64_round(v2, modifier); + v3 = XXH64_round(v3, key.lo); + v4 = XXH64_round(v4, key.hi); + + return XXH64_avalanche(XXH64_mergerounds(v1, v2, v3, v4)); +} + +static uint64_t pauth_computepac(CPUARMState *env, uint64_t data, + uint64_t modifier, ARMPACKey key) +{ + if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) { + return pauth_computepac_architected(data, modifier, key); + } else { + return pauth_computepac_impdef(data, modifier, key); + } +} + static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data) { @@ -292,7 +323,7 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, bot_bit = 64 - param.tsz; ext_ptr = deposit64(ptr, bot_bit, top_bit - bot_bit, ext); - pac = pauth_computepac(ext_ptr, modifier, *key); + pac = pauth_computepac(env, ext_ptr, modifier, *key); /* * Check if the ptr has good extension bits and corrupt the @@ -341,7 +372,7 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, uint64_t pac, orig_ptr, test; orig_ptr = pauth_original_ptr(ptr, param); - pac = pauth_computepac(orig_ptr, modifier, *key); + pac = pauth_computepac(env, orig_ptr, modifier, *key); bot_bit = 64 - param.tsz; top_bit = 64 - 8 * param.tbi; @@ -442,7 +473,7 @@ uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y) uint64_t pac; pauth_check_trap(env, arm_current_el(env), GETPC()); - pac = pauth_computepac(x, y, env->keys.apga); + pac = pauth_computepac(env, x, y, env->keys.apga); return pac & 0xffffffff00000000ull; }