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[209.51.188.17]) by mx.google.com with ESMTPS id n72si2568771ybf.240.2020.08.05.11.19.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 05 Aug 2020 11:19:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="sowj/PvI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k3O13-00078q-FX for patch@linaro.org; Wed, 05 Aug 2020 14:19:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k3Nym-0004PB-Ep for qemu-devel@nongnu.org; Wed, 05 Aug 2020 14:17:32 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:39054) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k3Nyj-0006Tx-Qh for qemu-devel@nongnu.org; Wed, 05 Aug 2020 14:17:32 -0400 Received: by mail-pj1-x1036.google.com with SMTP id f9so4779659pju.4 for ; Wed, 05 Aug 2020 11:17:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AeDpfxqkdAEXeD0Us9Svn7h86jElbTJX/muq5WTwNbc=; b=sowj/PvItMmu8NBwvfGGeqmrW1OX1jqRjIyWgAzoKIwV8FNfxYd9wnclVR70+vRkRS Jon4BlDzbt/dVJrbMcTyBJM/GxzmidudqoS8DBKBj2D9S6LhTPZGFCUogaJ4DZH5xhFf aj4lbeqK3fz6cN5ycfFqTveISpgW1AldVb/uiWyO09TA3TP2HKOsCApmdKKEtHLSKXW8 iVBqwbgp2ZbD5hFrxwyvq/n2/uqhrcT7xtsyE4mgXX2bZSa4sbpUuJVyP/61w7oKwKlU INCQMjkh5+/HLoqEGQRtlRnpaOdRcdFLWrIKzzlihL5KoJ0hJaGH1+9IBlJtObXZNI/7 S0IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AeDpfxqkdAEXeD0Us9Svn7h86jElbTJX/muq5WTwNbc=; b=gqeNYMF7zIpzZ2AiRRyywkjpWUzzF4+2wVOIN2wQN7n994QHOFMSb9aOrIx6QZswmW owxKqd6KIjr/TaVyDgp9Uu27yAESwRTrqpvEM8ONmfJFuVg90gmr0GTQDsTW/w6SiZux 7ZhIo+yb1PbAQgyr59sntIVcob1FjRYWTOJx78jiBv+Re9knTEK4mfyEcQGHH8dBCyDc iiOqfbzmQtrrPBXzo6GWOHPsv9/Nn/WHocLrdP/ymFaoJE1QFiPYMaYloUYp5p1nRMg8 ceEEm7OMTc/Fs1qN3dXo084BAKJC4827fhyFuu01u7jVfSEUnAysJwL86Gc2+ul1Uub5 0/OQ== X-Gm-Message-State: AOAM5312AF1EGsRX0ZRCHjtIj5wQEbNswvVfMYT1SgdVGyV2bn0MeCim OltNB0xPTOJCXKJ6ZBWahtfbgCPrztY= X-Received: by 2002:a17:902:40a:: with SMTP id 10mr4238883ple.180.1596651448072; Wed, 05 Aug 2020 11:17:28 -0700 (PDT) Received: from Rfoley-MA01.hsd1.ma.comcast.net ([2601:199:4480:60c0:38ab:50b1:ff8a:26ef]) by smtp.gmail.com with ESMTPSA id a15sm3670196pfo.185.2020.08.05.11.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2020 11:17:27 -0700 (PDT) From: Robert Foley To: qemu-devel@nongnu.org Subject: [PATCH v1 10/21] target/microblaze: add BQL to do_interrupt and cpu_exec_interrupt Date: Wed, 5 Aug 2020 14:12:52 -0400 Message-Id: <20200805181303.7822-11-robert.foley@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200805181303.7822-1-robert.foley@linaro.org> References: <20200805181303.7822-1-robert.foley@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=robert.foley@linaro.org; helo=mail-pj1-x1036.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.foley@linaro.org, peter.puhov@linaro.org, cota@braap.org, pbonzini@redhat.com, "Edgar E. Iglesias" , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec_interrupt. The purpose of this set of changes is to set the groundwork so that an arch could move towards removing the BQL from the cpu_handle_interrupt/exception paths. This approach was suggested by Paolo Bonzini. For reference, here are two key posts in the discussion, explaining the reasoning/benefits of this approach. https://lists.gnu.org/archive/html/qemu-devel/2020-07/msg08731.html https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00044.html Signed-off-by: Robert Foley --- target/microblaze/helper.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ab2ceeb055..ae8ff2bea4 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -32,10 +32,17 @@ void mb_cpu_do_interrupt(CPUState *cs) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; + bool bql = !qemu_mutex_iothread_locked(); + if (bql) { + qemu_mutex_lock_iothread(); + } cs->exception_index = -1; env->res_addr = RES_ADDR_NONE; env->regs[14] = env->sregs[SR_PC]; + if (bql) { + qemu_mutex_unlock_iothread(); + } } bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -113,6 +120,10 @@ void mb_cpu_do_interrupt(CPUState *cs) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; uint32_t t; + bool bql = !qemu_mutex_iothread_locked(); + if (bql) { + qemu_mutex_lock_iothread(); + } /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); @@ -123,6 +134,9 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_EXCP: if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n"); + if (bql) { + qemu_mutex_unlock_iothread(); + } return; } @@ -262,6 +276,9 @@ void mb_cpu_do_interrupt(CPUState *cs) cs->exception_index); break; } + if (bql) { + qemu_mutex_unlock_iothread(); + } } hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -291,6 +308,7 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; + qemu_mutex_lock_iothread(); if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sregs[SR_MSR] & MSR_IE) @@ -298,7 +316,9 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) && !(env->iflags & (D_FLAG | IMM_FLAG))) { cs->exception_index = EXCP_IRQ; mb_cpu_do_interrupt(cs); + qemu_mutex_unlock_iothread(); return true; } + qemu_mutex_unlock_iothread(); return false; }