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Wed, 29 Jul 2020 11:28:34 +0000 From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Date: Wed, 29 Jul 2020 16:57:59 +0530 Message-Id: <20200729112801.108985-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200729112801.108985-1-anup.patel@wdc.com> References: <20200729112801.108985-1-anup.patel@wdc.com> X-ClientProxiedBy: BM1PR01CA0166.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:68::36) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.56.183.175) by BM1PR01CA0166.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:68::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3239.17 via Frontend Transport; Wed, 29 Jul 2020 11:28:30 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [103.56.183.175] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 9d466722-dda5-457f-182e-08d833b2875f X-MS-TrafficTypeDiagnostic: DM6PR04MB5753: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:4941; 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envelope-from=prvs=47218c038=Anup.Patel@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/29 07:28:35 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, MSGID_FROM_MTA_HEADER=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The RISC-V spec allows implementations to provide trapped instruction opcode in MTVAL/STVAL CSR for illegal/virtual instruction traps. This is totally optional and most RISC-V implementations always set zero in the MTVAL/STVAL CSR for illegal/virtual instruction traps. When trapped instruction opcode is available in MTVAL/STVAL CSR, the M-mode runtime firmware (and Hypervisors) can skip unprivlege access for reading trapped instruction opcode which in-turn will speed-up the illegal/virtual instruction trap handling. This patch implements RISCV_FEATURE_TINST feature which when enabled provides original trapped instruction opcode in MTVAL/STVAL CSRs for illegal/virtual instruction trap. Signed-off-by: Anup Patel --- target/riscv/cpu.c | 7 +++++++ target/riscv/cpu.h | 11 ++++++++++- target/riscv/cpu_helper.c | 6 ++++++ target/riscv/translate.c | 14 +++++++++++++- 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eeb91f8513..ec098e445e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -317,6 +317,7 @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) { env->pc = data[0]; + env->trap_insn = data[1]; } static void riscv_cpu_reset(DeviceState *dev) @@ -332,6 +333,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause = 0; env->pc = env->resetvec; + env->trap_insn = 0; #endif cs->exception_index = EXCP_NONE; env->load_res = -1; @@ -387,6 +389,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_feature(env, RISCV_FEATURE_PMP); } + if (cpu->cfg.tinst) { + set_feature(env, RISCV_FEATURE_TINST); + } + /* If misa isn't set (rv32 and rv64 machines) set it here */ if (!env->misa) { /* Do some ISA extension error checking */ @@ -487,6 +493,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("tinst", RISCVCPU, cfg.tinst, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1bb5271511..33984539d7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -26,6 +26,12 @@ #define TCG_GUEST_DEFAULT_MO 0 +/* + * RISC-V-specific extra insn start words: + * 1: Original instruction opcode + */ +#define TARGET_INSN_START_EXTRA_WORDS 1 + #define TYPE_RISCV_CPU "riscv-cpu" #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -70,7 +76,8 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, - RISCV_FEATURE_MISA + RISCV_FEATURE_MISA, + RISCV_FEATURE_TINST }; #define PRIV_VERSION_1_10_0 0x00011000 @@ -97,6 +104,7 @@ struct CPURISCVState { target_ulong frm; target_ulong badaddr; + target_ulong trap_insn; target_ulong guest_phys_fault_addr; target_ulong priv_ver; @@ -264,6 +272,7 @@ typedef struct RISCVCPU { char *user_spec; bool mmu; bool pmp; + bool tinst; } cfg; } RISCVCPU; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index eccd80cfef..e4bd45d66a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -864,6 +864,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_STORE_PAGE_FAULT: tval = env->badaddr; break; + case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: + case RISCV_EXCP_ILLEGAL_INST: + if (riscv_feature(env, RISCV_FEATURE_TINST)) { + tval = env->trap_insn; + } + break; default: break; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d973b62e9..03954bff62 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,8 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + /* TCG op of the current insn_start. */ + TCGOp *insn_start; } DisasContext; #ifdef TARGET_RISCV64 @@ -717,6 +719,13 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, /* Include the auto-generated decoder for 16 bit insn */ #include "decode_insn16.inc.c" +static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) +{ + assert(ctx->insn_start != NULL); + tcg_set_insn_start_param(ctx->insn_start, 1, opc); + ctx->insn_start = NULL; +} + static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { /* check for compressed insn */ @@ -724,6 +733,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { + decode_save_opc(ctx, opcode); ctx->pc_succ_insn = ctx->base.pc_next + 2; if (!decode_insn16(ctx, opcode)) { /* fall back to old decoder */ @@ -734,6 +744,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) uint32_t opcode32 = opcode; opcode32 = deposit32(opcode32, 16, 16, translator_lduw(env, ctx->base.pc_next + 2)); + decode_save_opc(ctx, opcode32); ctx->pc_succ_insn = ctx->base.pc_next + 4; if (!decode_insn32(ctx, opcode32)) { gen_exception_illegal(ctx); @@ -773,7 +784,8 @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0); + ctx->insn_start = tcg_last_op(); } static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,