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Tue, 28 Jul 2020 15:08:44 +0000 (UTC) Received: from laptop.redhat.com (ovpn-112-203.ams2.redhat.com [10.36.112.203]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3AFA169328; Tue, 28 Jul 2020 15:08:29 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH for-5.2 v4 02/11] hw/arm/smmu-common: Add IOTLB helpers Date: Tue, 28 Jul 2020 17:08:06 +0200 Message-Id: <20200728150815.11446-3-eric.auger@redhat.com> In-Reply-To: <20200728150815.11446-1-eric.auger@redhat.com> References: <20200728150815.11446-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=207.211.31.81; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/28 10:31:13 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe@linaro.org, robh@kernel.org, robin.murphy@arm.com, mst@redhat.com, zhangfei.gao@foxmail.com, shameerali.kolothum.thodi@huawei.com, will@kernel.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add two helpers: one to lookup for a given IOTLB entry and one to insert a new entry. We also move the tracing there. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- include/hw/arm/smmu-common.h | 2 ++ hw/arm/smmu-common.c | 36 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3.c | 26 ++------------------------ hw/arm/trace-events | 5 +++-- 4 files changed, 43 insertions(+), 26 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index ca4a4b1ad1..1dceec5cb1 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -153,6 +153,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); #define SMMU_IOTLB_MAX_SIZE 256 +IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr iova); +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *entry); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index a3f9e47398..f3aa581f80 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -32,6 +32,42 @@ /* IOTLB Management */ +IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + hwaddr iova) +{ + SMMUIOTLBKey key = {.asid = cfg->asid, .iova = iova}; + IOMMUTLBEntry *entry = g_hash_table_lookup(bs->iotlb, &key); + + if (entry) { + cfg->iotlb_hits++; + trace_smmu_iotlb_lookup_hit(cfg->asid, iova, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)); + } else { + cfg->iotlb_misses++; + trace_smmu_iotlb_lookup_miss(cfg->asid, iova, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)); + } + return entry; +} + +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *entry) +{ + SMMUIOTLBKey *key = g_new0(SMMUIOTLBKey, 1); + + if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) { + smmu_iotlb_inv_all(bs); + } + + key->asid = cfg->asid; + key->iova = entry->iova; + trace_smmu_iotlb_insert(cfg->asid, entry->iova); + g_hash_table_insert(bs->iotlb, key, entry); +} + inline void smmu_iotlb_inv_all(SMMUState *s) { trace_smmu_iotlb_inv_all(); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 57a79df55b..cd2a2e7e14 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -636,7 +636,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, .addr_mask = ~(hwaddr)0, .perm = IOMMU_NONE, }; - SMMUIOTLBKey key, *new_key; qemu_mutex_lock(&s->mutex); @@ -675,16 +674,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, page_mask = (1ULL << (tt->granule_sz)) - 1; aligned_addr = addr & ~page_mask; - key.asid = cfg->asid; - key.iova = aligned_addr; - - cached_entry = g_hash_table_lookup(bs->iotlb, &key); + cached_entry = smmu_iotlb_lookup(bs, cfg, aligned_addr); if (cached_entry) { - cfg->iotlb_hits++; - trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr, - cfg->iotlb_hits, cfg->iotlb_misses, - 100 * cfg->iotlb_hits / - (cfg->iotlb_hits + cfg->iotlb_misses)); if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) { status = SMMU_TRANS_ERROR; if (event.record_trans_faults) { @@ -698,16 +689,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, goto epilogue; } - cfg->iotlb_misses++; - trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask, - cfg->iotlb_hits, cfg->iotlb_misses, - 100 * cfg->iotlb_hits / - (cfg->iotlb_hits + cfg->iotlb_misses)); - - if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) { - smmu_iotlb_inv_all(bs); - } - cached_entry = g_new0(IOMMUTLBEntry, 1); if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { @@ -753,10 +734,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, } status = SMMU_TRANS_ERROR; } else { - new_key = g_new0(SMMUIOTLBKey, 1); - new_key->asid = cfg->asid; - new_key->iova = aligned_addr; - g_hash_table_insert(bs->iotlb, new_key, cached_entry); + smmu_iotlb_insert(bs, cfg, cached_entry); status = SMMU_TRANS_SUCCESS; } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0acedcedc6..b808a1bfc1 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -14,6 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=%s" +smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" +smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" +smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=%d addr=0x%"PRIx64 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" @@ -46,8 +49,6 @@ smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d a smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =%d addr=0x%"PRIx64 smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d" -smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" -smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"