diff mbox series

[v2,3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c

Message ID 20200724002807.441147-4-richard.henderson@linaro.org
State Accepted
Commit 40eaa473611936445ae9c63841445cfa6e36840b
Headers show
Series target/riscv: NaN-boxing for multiple precison | expand

Commit Message

Richard Henderson July 24, 2020, 12:28 a.m. UTC 
Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/insn_trans/trans_rvf.inc.c | 4 ++++
 1 file changed, 4 insertions(+)

-- 
2.25.1

Comments

LIU Zhiwei July 24, 2020, 2:41 a.m. UTC | #1 
On 2020/7/24 8:28, Richard Henderson wrote:
> Make sure that all results from inline single-precision scalar

> operations are properly nan-boxed to 64-bits.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>   target/riscv/insn_trans/trans_rvf.inc.c | 4 ++++

>   1 file changed, 4 insertions(+)

>

> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c

> index c7057482e8..264d3139f1 100644

> --- a/target/riscv/insn_trans/trans_rvf.inc.c

> +++ b/target/riscv/insn_trans/trans_rvf.inc.c

> @@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)

>           tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],

>                               0, 31);

>       }

> +    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>       mark_fs_dirty(ctx);

>       return true;

>   }

> @@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)

>           tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);

>           tcg_temp_free_i64(t0);

>       }

> +    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>       mark_fs_dirty(ctx);

>       return true;

>   }

> @@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)

>           tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);

>           tcg_temp_free_i64(t0);

>       }

> +    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>       mark_fs_dirty(ctx);

>       return true;

>   }

> @@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)

>   #else

>       tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);

>   #endif

> +    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>   

>       mark_fs_dirty(ctx);

>       tcg_temp_free(t0);

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>


Zhiwei
Chih-Min Chao Aug. 6, 2020, 6:24 a.m. UTC | #2 
On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> Make sure that all results from inline single-precision scalar

> operations are properly nan-boxed to 64-bits.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/riscv/insn_trans/trans_rvf.inc.c | 4 ++++

>  1 file changed, 4 insertions(+)

>

> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c

> b/target/riscv/insn_trans/trans_rvf.inc.c

> index c7057482e8..264d3139f1 100644

> --- a/target/riscv/insn_trans/trans_rvf.inc.c

> +++ b/target/riscv/insn_trans/trans_rvf.inc.c

> @@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx,

> arg_fsgnj_s *a)

>          tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],

> cpu_fpr[a->rs1],

>                              0, 31);

>      }

> +    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>      mark_fs_dirty(ctx);

>      return true;

>  }

> @@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx,

> arg_fsgnjn_s *a)

>          tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);

>          tcg_temp_free_i64(t0);

>      }

> +    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>      mark_fs_dirty(ctx);

>      return true;

>  }

> @@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx,

> arg_fsgnjx_s *a)

>          tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);

>          tcg_temp_free_i64(t0);

>      }

> +    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>      mark_fs_dirty(ctx);

>      return true;

>  }

> @@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx,

> arg_fmv_w_x *a)

>  #else

>      tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);

>  #endif

> +    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>

>      mark_fs_dirty(ctx);

>      tcg_temp_free(t0);

> --

> 2.25.1

>

>

>

Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>


Chih-Min Chao
<div dir="ltr"><div dir="ltr"><div><br></div></div><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>&gt; wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Make sure that all results from inline single-precision scalar<br>
operations are properly nan-boxed to 64-bits.<br>
<br>
Signed-off-by: Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>&gt;<br>

---<br>
 target/riscv/insn_trans/trans_rvf.inc.c | 4 ++++<br>
 1 file changed, 4 insertions(+)<br>
<br>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c<br>
index c7057482e8..264d3139f1 100644<br>
--- a/target/riscv/insn_trans/trans_rvf.inc.c<br>
+++ b/target/riscv/insn_trans/trans_rvf.inc.c<br>
@@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)<br>
         tcg_gen_deposit_i64(cpu_fpr[a-&gt;rd], cpu_fpr[a-&gt;rs2], cpu_fpr[a-&gt;rs1],<br>
                             0, 31);<br>
     }<br>
+    gen_nanbox_s(cpu_fpr[a-&gt;rd], cpu_fpr[a-&gt;rd]);<br>
     mark_fs_dirty(ctx);<br>
     return true;<br>
 }<br>
@@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)<br>
         tcg_gen_deposit_i64(cpu_fpr[a-&gt;rd], t0, cpu_fpr[a-&gt;rs1], 0, 31);<br>
         tcg_temp_free_i64(t0);<br>
     }<br>
+    gen_nanbox_s(cpu_fpr[a-&gt;rd], cpu_fpr[a-&gt;rd]);<br>
     mark_fs_dirty(ctx);<br>
     return true;<br>
 }<br>
@@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)<br>
         tcg_gen_xor_i64(cpu_fpr[a-&gt;rd], cpu_fpr[a-&gt;rs1], t0);<br>
         tcg_temp_free_i64(t0);<br>
     }<br>
+    gen_nanbox_s(cpu_fpr[a-&gt;rd], cpu_fpr[a-&gt;rd]);<br>
     mark_fs_dirty(ctx);<br>
     return true;<br>
 }<br>
@@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)<br>
 #else<br>
     tcg_gen_extu_i32_i64(cpu_fpr[a-&gt;rd], t0);<br>
 #endif<br>
+    gen_nanbox_s(cpu_fpr[a-&gt;rd], cpu_fpr[a-&gt;rd]);<br>
<br>
     mark_fs_dirty(ctx);<br>
     tcg_temp_free(t0);<br>
-- <br>
2.25.1<br>
<br>
<br></blockquote><div><br></div><div>Reviewed-by: Chih-Min Chao &lt;<a href="mailto:chihmin.chao@sifive.com">chihmin.chao@sifive.com</a>&gt;</div><div><br></div><div><div dir="ltr" class="gmail_signature"><div dir="ltr"><span style="color:rgb(136,136,136)">Chih-Min Chao</span><div style="color:rgb(136,136,136)"></div></div></div></div><div> </div></div></div>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index c7057482e8..264d3139f1 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -167,6 +167,7 @@  static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
         tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
                             0, 31);
     }
+    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
     mark_fs_dirty(ctx);
     return true;
 }
@@ -183,6 +184,7 @@  static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
         tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
         tcg_temp_free_i64(t0);
     }
+    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
     mark_fs_dirty(ctx);
     return true;
 }
@@ -199,6 +201,7 @@  static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
         tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
         tcg_temp_free_i64(t0);
     }
+    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
     mark_fs_dirty(ctx);
     return true;
 }
@@ -369,6 +372,7 @@  static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
 #else
     tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
 #endif
+    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
 
     mark_fs_dirty(ctx);
     tcg_temp_free(t0);