| Message ID | 20200724002807.441147-3-richard.henderson@linaro.org |
|---|---|
| State | Accepted |
| Commit | d36a86d01e67792c51dd2a82360cda012bde9442 |
| Headers | show |
| Series | target/riscv: NaN-boxing for multiple precison | expand |
On 2020/7/24 8:28, Richard Henderson wrote: > Do not depend on the RVD extension, take input and output via > TCGv_i64 instead of fpu regno. Move the function to translate.c > so that it can be used in multiple trans_*.inc.c files. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/riscv/insn_trans/trans_rvf.inc.c | 16 +--------------- > target/riscv/translate.c | 11 +++++++++++ > 2 files changed, 12 insertions(+), 15 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c > index 3bfd8881e7..c7057482e8 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -23,20 +23,6 @@ > return false; \ > } while (0) > > -/* > - * RISC-V requires NaN-boxing of narrower width floating > - * point values. This applies when a 32-bit value is > - * assigned to a 64-bit FP register. Thus this does not > - * apply when the RVD extension is not present. > - */ > -static void gen_nanbox_fpr(DisasContext *ctx, int regno) > -{ > - if (has_ext(ctx, RVD)) { > - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], > - MAKE_64BIT_MASK(32, 32)); > - } > -} > - > static bool trans_flw(DisasContext *ctx, arg_flw *a) > { > TCGv t0 = tcg_temp_new(); > @@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) > tcg_gen_addi_tl(t0, t0, a->imm); > > tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); > - gen_nanbox_fpr(ctx, a->rd); > + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); > > tcg_temp_free(t0); > mark_fs_dirty(ctx); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 9632e79cf3..12a746da97 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) > return ctx->misa & ext; > } > > +/* > + * RISC-V requires NaN-boxing of narrower width floating point values. > + * This applies when a 32-bit value is assigned to a 64-bit FP register. > + * For consistency and simplicity, we nanbox results even when the RVD > + * extension is not present. > + */ > +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) > +{ > + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); > +} > + If possible, +static void gen_nanbox(TCGv_i64 out, TCGv_i64 in, uint32_t flen) +{ + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(flen, 64 - flen)); +} + Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Zhiwei > static void generate_exception(DisasContext *ctx, int excp) > { > tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson < richard.henderson@linaro.org> wrote: > Do not depend on the RVD extension, take input and output via > TCGv_i64 instead of fpu regno. Move the function to translate.c > so that it can be used in multiple trans_*.inc.c files. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/riscv/insn_trans/trans_rvf.inc.c | 16 +--------------- > target/riscv/translate.c | 11 +++++++++++ > 2 files changed, 12 insertions(+), 15 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c > b/target/riscv/insn_trans/trans_rvf.inc.c > index 3bfd8881e7..c7057482e8 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -23,20 +23,6 @@ > return false; \ > } while (0) > > -/* > - * RISC-V requires NaN-boxing of narrower width floating > - * point values. This applies when a 32-bit value is > - * assigned to a 64-bit FP register. Thus this does not > - * apply when the RVD extension is not present. > - */ > -static void gen_nanbox_fpr(DisasContext *ctx, int regno) > -{ > - if (has_ext(ctx, RVD)) { > - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], > - MAKE_64BIT_MASK(32, 32)); > - } > -} > - > static bool trans_flw(DisasContext *ctx, arg_flw *a) > { > TCGv t0 = tcg_temp_new(); > @@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) > tcg_gen_addi_tl(t0, t0, a->imm); > > tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); > - gen_nanbox_fpr(ctx, a->rd); > + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); > > tcg_temp_free(t0); > mark_fs_dirty(ctx); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 9632e79cf3..12a746da97 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t > ext) > return ctx->misa & ext; > } > > +/* > + * RISC-V requires NaN-boxing of narrower width floating point values. > + * This applies when a 32-bit value is assigned to a 64-bit FP register. > + * For consistency and simplicity, we nanbox results even when the RVD > + * extension is not present. > + */ > +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) > +{ > + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); > +} > + > static void generate_exception(DisasContext *ctx, int excp) > { > tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); > -- > 2.25.1 > > > Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> <div dir="ltr"><div dir="ltr"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr"><br></div></div></div></div><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson <<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Do not depend on the RVD extension, take input and output via<br> TCGv_i64 instead of fpu regno. Move the function to translate.c<br> so that it can be used in multiple trans_*.inc.c files.<br> <br> Signed-off-by: Richard Henderson <<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>><br> ---<br> target/riscv/insn_trans/trans_rvf.inc.c | 16 +---------------<br> target/riscv/translate.c | 11 +++++++++++<br> 2 files changed, 12 insertions(+), 15 deletions(-)<br> <br> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c<br> index 3bfd8881e7..c7057482e8 100644<br> --- a/target/riscv/insn_trans/trans_rvf.inc.c<br> +++ b/target/riscv/insn_trans/trans_rvf.inc.c<br> @@ -23,20 +23,6 @@<br> return false; \<br> } while (0)<br> <br> -/*<br> - * RISC-V requires NaN-boxing of narrower width floating<br> - * point values. This applies when a 32-bit value is<br> - * assigned to a 64-bit FP register. Thus this does not<br> - * apply when the RVD extension is not present.<br> - */<br> -static void gen_nanbox_fpr(DisasContext *ctx, int regno)<br> -{<br> - if (has_ext(ctx, RVD)) {<br> - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],<br> - MAKE_64BIT_MASK(32, 32));<br> - }<br> -}<br> -<br> static bool trans_flw(DisasContext *ctx, arg_flw *a)<br> {<br> TCGv t0 = tcg_temp_new();<br> @@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)<br> tcg_gen_addi_tl(t0, t0, a->imm);<br> <br> tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);<br> - gen_nanbox_fpr(ctx, a->rd);<br> + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);<br> <br> tcg_temp_free(t0);<br> mark_fs_dirty(ctx);<br> diff --git a/target/riscv/translate.c b/target/riscv/translate.c<br> index 9632e79cf3..12a746da97 100644<br> --- a/target/riscv/translate.c<br> +++ b/target/riscv/translate.c<br> @@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)<br> return ctx->misa & ext;<br> }<br> <br> +/*<br> + * RISC-V requires NaN-boxing of narrower width floating point values.<br> + * This applies when a 32-bit value is assigned to a 64-bit FP register.<br> + * For consistency and simplicity, we nanbox results even when the RVD<br> + * extension is not present.<br> + */<br> +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)<br> +{<br> + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));<br> +}<br> +<br> static void generate_exception(DisasContext *ctx, int excp)<br> {<br> tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);<br> -- <br> 2.25.1<br> <br> <br></blockquote><div><br></div><div>Reviewed-by: Chih-Min Chao <<a href="mailto:chihmin.chao@sifive.com">chihmin.chao@sifive.com</a>><br></div></div></div>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 3bfd8881e7..c7057482e8 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -23,20 +23,6 @@ return false; \ } while (0) -/* - * RISC-V requires NaN-boxing of narrower width floating - * point values. This applies when a 32-bit value is - * assigned to a 64-bit FP register. Thus this does not - * apply when the RVD extension is not present. - */ -static void gen_nanbox_fpr(DisasContext *ctx, int regno) -{ - if (has_ext(ctx, RVD)) { - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], - MAKE_64BIT_MASK(32, 32)); - } -} - static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv t0 = tcg_temp_new(); @@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - gen_nanbox_fpr(ctx, a->rd); + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); tcg_temp_free(t0); mark_fs_dirty(ctx); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9632e79cf3..12a746da97 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa & ext; } +/* + * RISC-V requires NaN-boxing of narrower width floating point values. + * This applies when a 32-bit value is assigned to a 64-bit FP register. + * For consistency and simplicity, we nanbox results even when the RVD + * extension is not present. + */ +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
Do not depend on the RVD extension, take input and output via TCGv_i64 instead of fpu regno. Move the function to translate.c so that it can be used in multiple trans_*.inc.c files. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvf.inc.c | 16 +--------------- target/riscv/translate.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) -- 2.25.1