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d="scan'208";a="142511937" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 14 Jul 2020 08:42:31 +0800 IronPort-SDR: 7gjOg1RyGNSVqHlweb7o3qEojz/Dlml+xFyNtlQfIEKFUyF/FdAHCjcSncc4exp79ZUt7DfNOY qVjjHHApOiuwv1cv/kM/fwYM8aQKzRYv4= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2020 17:30:59 -0700 IronPort-SDR: OCOTQCM23AF5VsabEGLKEAWrZ6Mg8KIMxb6R5pxgBG2IrRzjA/Z2+nw+K9EGheSbVroCmzu0O4 TrQUWQqVGPrw== WDCIronportException: Internal Received: from usa002626.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.57.178]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Jul 2020 17:42:31 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL 15/15] target/riscv: Fix pmp NA4 implementation Date: Mon, 13 Jul 2020 17:32:54 -0700 Message-Id: <20200714003254.4044149-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200714003254.4044149-1-alistair.francis@wdc.com> References: <20200714003254.4044149-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=457b4eeb6=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/13 20:42:28 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Alexandre Mergnat Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexandre Mergnat The end address calculation for NA4 mode is wrong because the address used isn't shifted. It doesn't watch 4 bytes but a huge range because the end address calculation is wrong. The solution is to use the shifted address calculated for start address variable. Modifications are tested on Zephyr OS userspace test suite which works for other RISC-V boards (E31 and E34 core). Signed-off-by: Alexandre Mergnat Reviewed-by: Alistair Francis Message-id: 20200706084550.24117-1-amergnat@baylibre.com Message-Id: <20200706084550.24117-1-amergnat@baylibre.com> [ Changes by AF: - Improve the commit title and message ] Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 9418660f1b..2a2b9f5363 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -171,7 +171,7 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) case PMP_AMATCH_NA4: sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ - ea = (this_addr + 4u) - 1u; + ea = (sa + 4u) - 1u; break; case PMP_AMATCH_NAPOT: