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[209.51.188.17]) by mx.google.com with ESMTPS id l131si8667378ybc.259.2020.07.11.10.09.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 11 Jul 2020 10:09:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UNd4SAMg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juJ04-0006iE-1O for patch@linaro.org; Sat, 11 Jul 2020 13:09:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIyS-0003NM-8E for qemu-devel@nongnu.org; Sat, 11 Jul 2020 13:07:40 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:46581) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1juIyQ-0006hI-Az for qemu-devel@nongnu.org; Sat, 11 Jul 2020 13:07:39 -0400 Received: by mail-wr1-x444.google.com with SMTP id r12so8945832wrj.13 for ; Sat, 11 Jul 2020 10:07:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OO5QET4LtmEfAVYxPO2I8IFA0YsWV4r+MxTZRfSVWs0=; b=UNd4SAMgmNKE4lxa3rqbPw26qbXY7peJGpfCyPDQLTQHNgydfzOD0Tl/m3JBkKOJpc AdPq/quto9L4pFuWf/oQ8UH43vPadSywzZSrPWLbhpy+m7GA5OeJD+Rm5hyRVSsbllYl On2SizG4QZl4NZRe8Y2WEYiZ0UTC+5GwuEl2vCD25yt9grK2BsJoEx7O2lF6VgX5mp7D PRoPAZSRw4EPkPFW3pZuyckOqAbXQRmvYWEKo1PaGKJ4sOrU/wkEanEvGXT2TmRwpgo6 GnVmKI2roWaS05lBPZaXY4IkHqBCI4oL6erxC758i+VJKbqNemuUudAVao+lPHJ7D3N0 ke5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OO5QET4LtmEfAVYxPO2I8IFA0YsWV4r+MxTZRfSVWs0=; b=e82oE2qj8c9vUogXp77P2BW+cMPCKCaUQrVNfFBkCBC088TxGi+8yiHqFvlo6s0fUC fjSZsGDjiJKXlKMyahddWdad8H0lp7Pka3KABrF3NVF1WYpnuNmUwef42OJ4tFJkjYei jbhSIRdB9IM4Hqxa6L+zknwgAfw5Lph74LQ6nwpddwR8ue3XB1PZ8Zt0OtvDirMY6T0t pXwnsXfcjkLHInWU6UVIFCSg0i2e1dwGFQg9h89qsABTqrMbfAvBtvt2S1lxLrtZzzzV nChTLVTGdIl2PgPdPOyGCmMEAAma/m6V6CbXNpuLzorLcj0Q02SDE0uSzdHq8lIvh9bq A3HQ== X-Gm-Message-State: AOAM530FvCqADDgloURlsSiGqfzPVthEqz7Xm43cq7L+xsDKkPWf286P LeMh+gOHVYisytzMCtmOjot7aQ== X-Received: by 2002:adf:eec8:: with SMTP id a8mr73665988wrp.421.1594487256562; Sat, 11 Jul 2020 10:07:36 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 65sm17571494wre.6.2020.07.11.10.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jul 2020 10:07:32 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 514111FF8C; Sat, 11 Jul 2020 18:07:32 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Subject: [PULL v2 42/50] docs/devel: convert and update MTTCG design document Date: Sat, 11 Jul 2020 18:07:24 +0100 Message-Id: <20200711170732.26213-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200711170732.26213-1-alex.bennee@linaro.org> References: <20200711170732.26213-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do a light conversion to .rst and clean-up some of the language at the start now MTTCG has been merged for a while. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20200709141327.14631-2-alex.bennee@linaro.org> -- 2.20.1 diff --git a/docs/devel/index.rst b/docs/devel/index.rst index bb8238c5d6..4ecaea3643 100644 --- a/docs/devel/index.rst +++ b/docs/devel/index.rst @@ -23,6 +23,7 @@ Contents: decodetree secure-coding-practices tcg + multi-thread-tcg tcg-plugins bitops reset diff --git a/docs/devel/multi-thread-tcg.txt b/docs/devel/multi-thread-tcg.rst similarity index 90% rename from docs/devel/multi-thread-tcg.txt rename to docs/devel/multi-thread-tcg.rst index 3c85ac0eab..42158b77c7 100644 --- a/docs/devel/multi-thread-tcg.txt +++ b/docs/devel/multi-thread-tcg.rst @@ -1,15 +1,17 @@ -Copyright (c) 2015-2016 Linaro Ltd. +.. + Copyright (c) 2015-2020 Linaro Ltd. -This work is licensed under the terms of the GNU GPL, version 2 or -later. See the COPYING file in the top-level directory. + This work is licensed under the terms of the GNU GPL, version 2 or + later. See the COPYING file in the top-level directory. Introduction ============ -This document outlines the design for multi-threaded TCG system-mode -emulation. The current user-mode emulation mirrors the thread -structure of the translated executable. Some of the work will be -applicable to both system and linux-user emulation. +This document outlines the design for multi-threaded TCG (a.k.a MTTCG) +system-mode emulation. user-mode emulation has always mirrored the +thread structure of the translated executable although some of the +changes done for MTTCG system emulation have improved the stability of +linux-user emulation. The original system-mode TCG implementation was single threaded and dealt with multiple CPUs with simple round-robin scheduling. This @@ -21,9 +23,18 @@ vCPU Scheduling =============== We introduce a new running mode where each vCPU will run on its own -user-space thread. This will be enabled by default for all FE/BE -combinations that have had the required work done to support this -safely. +user-space thread. This is enabled by default for all FE/BE +combinations where the host memory model is able to accommodate the +guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the +guest has had the required work done to support this safely +(TARGET_SUPPORTS_MTTCG). + +System emulation will fall back to the original round robin approach +if: + +* forced by --accel tcg,thread=single +* enabling --icount mode +* 64 bit guests on 32 bit hosts (TCG_OVERSIZED_GUEST) In the general case of running translated code there should be no inter-vCPU dependencies and all vCPUs should be able to run at full @@ -61,7 +72,9 @@ have their block-to-block jumps patched. Global TCG State ---------------- -### User-mode emulation +User-mode emulation +~~~~~~~~~~~~~~~~~~~ + We need to protect the entire code generation cycle including any post generation patching of the translated code. This also implies a shared translation buffer which contains code running on all cores. Any @@ -78,9 +91,11 @@ patching. Code generation is serialised with mmap_lock(). -### !User-mode emulation +!User-mode emulation +~~~~~~~~~~~~~~~~~~~~ + Each vCPU has its own TCG context and associated TCG region, thereby -requiring no locking. +requiring no locking during translation. Translation Blocks ------------------ @@ -92,6 +107,7 @@ including: - debugging operations (breakpoint insertion/removal) - some CPU helper functions + - linux-user spawning it's first thread This is done with the async_safe_run_on_cpu() mechanism to ensure all vCPUs are quiescent when changes are being made to shared global @@ -250,8 +266,10 @@ to enforce a particular ordering of memory operations from the point of view of external observers (e.g. another processor core). They can apply to any memory operations as well as just loads or stores. -The Linux kernel has an excellent write-up on the various forms of -memory barrier and the guarantees they can provide [1]. +The Linux kernel has an excellent `write-up +` +on the various forms of memory barrier and the guarantees they can +provide. Barriers are often wrapped around synchronisation primitives to provide explicit memory ordering semantics. However they can be used @@ -352,7 +370,3 @@ an exclusive lock which ensures all emulation is serialised. While the atomic helpers look good enough for now there may be a need to look at solutions that can more closely model the guest architectures semantics. - -========== - -[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/memory-barriers.txt