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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id p9sm2144569ejd.50.2020.06.30.07.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2020 07:52:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Aurelien Jarno , Yunqiang Su , qemu-devel@nongnu.org Subject: [PATCH v2 5/6] hw/mips/malta: Verify malta-strict machine uses correct DIMM sizes Date: Tue, 30 Jun 2020 16:52:35 +0200 Message-Id: <20200630145236.27529-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200630145236.27529-1-f4bug@amsat.org> References: <20200630145236.27529-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::641; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Markovic , Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The machine has 4 DIMM slots. Each DIMM must be a power of 2. Add a check the total RAM is a good combination of DIMMs. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 209237d066..63c1d5ea5f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -71,6 +71,8 @@ #define MAX_IDE_BUS 2 +#define DIMM_SLOTS_COUNT 4 + #define TYPE_MALTA_MACHINE MACHINE_TYPE_NAME("malta-base") #define MALTA_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(MaltaMachineClass, (klass), TYPE_MALTA_MACHINE) @@ -82,6 +84,7 @@ typedef struct MaltaMachineClass { MachineClass parent_obj; /* Public */ ram_addr_t max_ramsize; + bool verify_dimm_sizes; } MaltaMachineClass; typedef struct { @@ -1260,6 +1263,12 @@ void mips_malta_init(MachineState *machine) /* create CPU */ mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); + if (mmc->verify_dimm_sizes && ctpop64(ram_size) > DIMM_SLOTS_COUNT) { + error_report("RAM size must be the combination of %d powers of 2", + DIMM_SLOTS_COUNT); + exit(1); + } + /* * The GT-64120A north bridge accepts at most 256 MiB per SCS for * address decoding, so we have a maximum of 1 GiB. We deliberately @@ -1493,6 +1502,7 @@ static void malta_machine_strict_class_init(ObjectClass *oc, void *data) #endif mc->default_ram_size = 32 * MiB; mmc->max_ramsize = 256 * MiB; /* 32 MByte PC100 SDRAM DIMMs x 4 slots */ + mmc->verify_dimm_sizes = true; }; static const TypeInfo malta_machine_types[] = {