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[PULL,07/32] target/riscv: Set access as data_load when validating stage-2 PTEs

Message ID 20200619062518.1718523-8-alistair.francis@wdc.com
State New
Headers show
Series [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register | expand

Commit Message

Alistair Francis June 19, 2020, 6:24 a.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 62fe1ecc8f..eda7057663 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -435,7 +435,7 @@  restart:
             hwaddr vbase;
 
             /* Do the second stage translation on the base PTE address. */
-            get_physical_address(env, &vbase, &vbase_prot, base, access_type,
+            get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
                                  mmu_idx, false, true);
 
             pte_addr = vbase + idx * ptesize;