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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id h15sm5440902pgl.12.2020.06.04.21.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 21:17:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/17] linux-user/aarch64: Implement PROT_MTE Date: Thu, 4 Jun 2020 21:17:27 -0700 Message-Id: <20200605041733.415188-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200605041733.415188-1-richard.henderson@linaro.org> References: <20200605041733.415188-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remember the PROT_MTE bit as PAGE_TARGET_2. Otherwise this does not yet have effect. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 + linux-user/syscall_defs.h | 1 + linux-user/mmap.c | 20 ++++++++++++-------- 3 files changed, 14 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 3cac7750e4..7ff10a8b08 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -286,6 +286,7 @@ extern intptr_t qemu_host_page_mask; #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 +#define PAGE_TARGET_2 0x0100 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 36bdafb3f1..f2bfa3b17f 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1196,6 +1196,7 @@ struct target_winsize { #ifdef TARGET_AARCH64 #define TARGET_PROT_BTI 0x10 +#define TARGET_PROT_MTE 0x20 #endif /* Common */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index fdd55986a1..b5618c40bd 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -84,18 +84,22 @@ static int validate_prot_to_pageflags(int *host_prot, int prot) | (prot & PROT_EXEC ? PROT_READ : 0); #ifdef TARGET_AARCH64 - /* - * The PROT_BTI bit is only accepted if the cpu supports the feature. - * Since this is the unusual case, don't bother checking unless - * the bit has been requested. If set and valid, record the bit - * within QEMU's page_flags as PAGE_TARGET_1. - */ - if (prot & TARGET_PROT_BTI) { + { ARMCPU *cpu = ARM_CPU(thread_cpu); - if (cpu_isar_feature(aa64_bti, cpu)) { + /* + * The PROT_BTI bit is only accepted if the cpu supports the feature. + * If set and valid, record the bit within QEMU's page_flags + * as PAGE_TARGET_1. + */ + if ((prot & TARGET_PROT_BTI) && cpu_isar_feature(aa64_bti, cpu)) { valid |= TARGET_PROT_BTI; page_flags |= PAGE_TARGET_1; } + /* Similarly for the PROT_MTE bit; set PAGE_TARGET_2. */ + if ((prot & TARGET_PROT_MTE) && cpu_isar_feature(aa64_mte, cpu)) { + valid |= TARGET_PROT_MTE; + page_flags |= PAGE_TARGET_2; + } } #endif