From patchwork Wed Jun 3 01:13:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187424 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp75963ilo; Tue, 2 Jun 2020 18:24:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxMkH2ClyYWRxMzPpJGpKGi43fNd91jqY9mCrTrGbPiTTb3g2D1iznTjzRARN+jjkXvND4t X-Received: by 2002:a25:d8d5:: with SMTP id p204mr33209632ybg.28.1591147476903; Tue, 02 Jun 2020 18:24:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591147476; cv=none; d=google.com; s=arc-20160816; b=SeOw0mU8eSoCTh9whsE9a01+2YFOv+Ap1cldAweIS72ZVf2UKm2u+RGtI+H10LI4Vz nNopvvaHC1HEDUYpdRdqAZN11IXANzkj/fBpQWM79fIbZwNz0jRkk1kPC/T4rH1Zcopp pJu81Ko/cbbbzolyPkJqM3jIlRPU6Wtrol3971ZGPOk/G9iUobX2RGv9uB1UFzhK6ND2 Wv4d+y4eAE4NmLhpMkZ+4JugkSv2SsH+kWdSi2j5fhztvPAUG0nNLvRJ08/A/VUCwtDe XPVg6GuQwVu8bHlyeaUGu5PRdo+BtBuqkeIsRfNXRJkD0yULtye7xA84NLkI9Ynp6x62 pfLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hOZXrSo9cXF1wY4dgGHftC4urn5UGRE1IwLPUAUKWmU=; b=Ma3YbSWedtaMQ8M+ncjydQ0eEDDZIAtWWg7QV8pnPQH3sYVRogPKBTl8t3wHtaCiNX 4+/INxsrDW00aEj2jtdW0MKmmr68uy+QRW2LtR6Px1jkyIsrsbMfcn8OnwSWZw8SQQQP X6Kb9Zi5+QFbh6TtiTziBkt2RBGiPdOziZXYRGxJ9pdFekiOnZjoxoJM7k/lxcQietXr gdwzviAaRS69yeQ5gkAfmnid0FjQT0MosjRsfHDOXkhcYtD3P96av3N790UrXD2WZcH9 dEEE1fkWYRPIix9qw0h0yEH5YWNUCN+r0vchrmpgxYpsjMV6jGzrJgq5T6jgJRGI0jRq +h6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MvVqF6OB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m11si349187ybm.322.2020.06.02.18.24.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 Jun 2020 18:24:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MvVqF6OB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgI8y-0008Qb-Be for patch@linaro.org; Tue, 02 Jun 2020 21:24:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgHyf-0004T1-4Q for qemu-devel@nongnu.org; Tue, 02 Jun 2020 21:13:57 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:38987) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jgHye-0003ds-7M for qemu-devel@nongnu.org; Tue, 02 Jun 2020 21:13:56 -0400 Received: by mail-pg1-x542.google.com with SMTP id w20so546267pga.6 for ; Tue, 02 Jun 2020 18:13:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hOZXrSo9cXF1wY4dgGHftC4urn5UGRE1IwLPUAUKWmU=; b=MvVqF6OBkeoC7W7h08RMRuLfXBstRCnyDWGZZBg0/lIKMj0flbgH6EwhwJtk7aCiDM 1IdN6FD6z7YqYNJl0nsS9Y5vmcbmILfZVtwPpujLKOohSG1a745yCeZlawFZpdW63oHm dzN1wPJ4XLHYG39f3VsDzDDnJCvnOWxWRZjCi7Ags7+cJagoTbzAXYXUbmbZgiml89Mu wmOAi4C9EF9GI1u/p2gbQlNwnuThGkiAMFIJUSXXfsw5RrcGP/DWeojXfYG09DQgGx/5 audiKz/+aj4pnf2XwT9PtcDfXNqksim8x4fQsG2T465afPVdlT5eew5p4PByTC52zvBy 51sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hOZXrSo9cXF1wY4dgGHftC4urn5UGRE1IwLPUAUKWmU=; b=YWuARX6vShzWLmBHTnJJhxqde1peapoSZ1jslZU7FYlvMvgxnciP/sqoxsjWZ8bMxV Jsz9SAGgf/8pUVLeu6KqHurJ7YbH6jNNTt6NCpKn0BcyEFf52KmAMzsrYLFnYwAag7wz IUaxIyoX6a7jMQTqjwn3Zij4HSamN32sGDGdj7wrQQCtuvxGhYCMBeHUHlR7mSuPCuGj i6p9UGI0j7gicjlH3u++Whq8rvNh9/tPGtg9EEbX0wf8Ltj6lEkliCbbEzJBcstCxy03 7e5MhWB6vHm9fxT1s3xHiCjpz3mwUo7v/n9S7OlOp8TToBTD1hrBBlzbO3/iJLaUTq0r G0DA== X-Gm-Message-State: AOAM533BlW8i9wJwOjZmYh6KEML5/QXNiZ+8tKHnW7W7s3lfr9mrgzpE +s6jXPkvifH7q6kvN8qqxiwJq62JMNs= X-Received: by 2002:a17:90a:c293:: with SMTP id f19mr1350383pjt.91.1591146834107; Tue, 02 Jun 2020 18:13:54 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id 3sm290067pfe.85.2020.06.02.18.13.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 18:13:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 27/42] target/arm: Add helper_mte_check_zva Date: Tue, 2 Jun 2020 18:13:02 -0700 Message-Id: <20200603011317.473934-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200603011317.473934-1-richard.henderson@linaro.org> References: <20200603011317.473934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use a special helper for DC_ZVA, rather than the more general mte_checkN. Leave the helper blank for now. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 106 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 16 +++++- 3 files changed, 122 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 005af678c7..5b0b699a50 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -106,6 +106,7 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(mte_checkN, TCG_CALL_NO_WG, i64, env, i32, i64) +DEF_HELPER_FLAGS_3(mte_check_zva, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index c8a523ed4e..175da11e01 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -661,3 +661,109 @@ uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) { return mte_checkN(env, desc, ptr, GETPC()); } + +/* + * Perform an MTE checked access for DC_ZVA. + */ +uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + uintptr_t ra = GETPC(); + int log2_dcz_bytes, log2_tag_bytes; + int mmu_idx, bit55; + intptr_t dcz_bytes, tag_bytes, i; + void *mem; + uint64_t ptr_tag, mem_tag, align_ptr; + + bit55 = extract64(ptr, 55, 1); + + /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */ + if (unlikely(!tbi_check(desc, bit55))) { + return ptr; + } + + ptr_tag = allocation_tag_from_addr(ptr); + + if (tcma_check(desc, bit55, ptr_tag)) { + goto done; + } + + /* + * In arm_cpu_realizefn, we asserted that dcz > LOG2_TAG_GRANULE+1, + * i.e. 32 bytes, which is an unreasonably small dcz anyway, to make + * sure that we can access one complete tag byte here. + */ + log2_dcz_bytes = env_archcpu(env)->dcz_blocksize + 2; + log2_tag_bytes = log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); + dcz_bytes = (intptr_t)1 << log2_dcz_bytes; + tag_bytes = (intptr_t)1 << log2_tag_bytes; + align_ptr = ptr & -dcz_bytes; + + /* + * Trap if accessing an invalid page. DC_ZVA requires that we supply + * the original pointer for an invalid page. But watchpoints require + * that we probe the actual space. So do both. + */ + mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); + (void) probe_write(env, ptr, 1, mmu_idx, ra); + mem = allocation_tag_mem(env, mmu_idx, align_ptr, MMU_DATA_STORE, + dcz_bytes, MMU_DATA_LOAD, tag_bytes, ra); + if (!mem) { + goto done; + } + + /* + * Unlike the reasoning for checkN, DC_ZVA is always aligned, and thus + * it is quite easy to perform all of the comparisons at once without + * any extra masking. + * + * The most common zva block size is 64; some of the thunderx cpus use + * a block size of 128. For user-only, aarch64_max_initfn will set the + * block size to 512. Fill out the other cases for future-proofing. + * + * In order to be able to find the first miscompare later, we want the + * tag bytes to be in little-endian order. + */ + switch (log2_tag_bytes) { + case 0: /* zva_blocksize 32 */ + mem_tag = *(uint8_t *)mem; + ptr_tag *= 0x11u; + break; + case 1: /* zva_blocksize 64 */ + mem_tag = cpu_to_le16(*(uint16_t *)mem); + ptr_tag *= 0x1111u; + break; + case 2: /* zva_blocksize 128 */ + mem_tag = cpu_to_le32(*(uint32_t *)mem); + ptr_tag *= 0x11111111u; + break; + case 3: /* zva_blocksize 256 */ + mem_tag = cpu_to_le64(*(uint64_t *)mem); + ptr_tag *= 0x1111111111111111ull; + break; + + default: /* zva_blocksize 512, 1024, 2048 */ + ptr_tag *= 0x1111111111111111ull; + i = 0; + do { + mem_tag = cpu_to_le64(*(uint64_t *)(mem + i)); + if (unlikely(mem_tag != ptr_tag)) { + goto fail; + } + i += 8; + align_ptr += 16 * TAG_GRANULE; + } while (i < tag_bytes); + goto done; + } + + if (likely(mem_tag == ptr_tag)) { + goto done; + } + + fail: + /* Locate the first nibble that differs. */ + i = ctz64(mem_tag ^ ptr_tag) >> 4; + mte_check_fail(env, mmu_idx, align_ptr + i * TAG_GRANULE, ra); + + done: + return useronly_clean_ptr(ptr); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f40eee5a14..c7deeca86a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1848,7 +1848,21 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. */ - tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); + if (s->mte_active[0]) { + TCGv_i32 t_desc; + int desc = 0; + + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + t_desc = tcg_const_i32(desc); + + tcg_rt = new_tmp_a64(s); + gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt)); + tcg_temp_free_i32(t_desc); + } else { + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); + } gen_helper_dc_zva(cpu_env, tcg_rt); return; default: