From patchwork Wed Jun 3 01:12:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187417 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp74302ilo; Tue, 2 Jun 2020 18:21:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJHn3v90Q7hUHyiRTMgzgU/IIAC9w/330fpxZhNF7pgCM/O6xDtj0TIdl3484XcwFBvVmV X-Received: by 2002:a5b:949:: with SMTP id x9mr10387202ybq.222.1591147293727; Tue, 02 Jun 2020 18:21:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591147293; cv=none; d=google.com; s=arc-20160816; b=qxnixH3nns7aY0oy/5/IalYtDzG1i8cWV3a5WxTSqqFpn9PbBkbmLccteJb113WhFe hnaiDhODwtMgS1BlqfkImrgv2zXYz/Vr2v6MqdhfGfKLcVlTJjOrGQ9/1SeAhGCWztz8 MlKpYCz+UluL3JdvcYfdTz8UFTuGpnuvQW40g/3fDNQ0hXPwDR8dzsh48SWV1Uf/785Z 11I4eyEXOIMjE7qMOsWhNXa6U6WBpy0ekWCh0cFPiKGXMfPR8a2Xmig8nzObS1KSv+7t d86+S1wLSw3HBjmECUpQUz0q37p8LkQeCXvYJ26g/IEjatCEwfQI7WQGctIJKnh1bpiK ocbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0EIkcVZM7CTGPx7yRFPLzi2q/BnEPgFyUzrQe3RUVmw=; b=vSI8PRgD5eWEtmkBTDG3/yFofn1AqPXe3IteUYov4/e7NS29nr/7E3VVsZi8LlfZbe rZyPuyvqCiQkC6oNW64utZe5MOHOAi9zujG10PiN0O2KgMao0B/iNokp4Knczb0K/m2a zb5abNt67d6TkN5No4Fz0SWaT9S4wG/ELvDd3XObxYPpsNYSoT1wn4w2imPOzoF1d9d5 00SWxhtjsLb5SZigeDWoqw3Ko67EYgaxBO39R4OPFSs+kWPXfuniF8EtYA32+y5ds2UC 7rE9bxvEYBhrr0aFOcVgwsxiRnDQdkGry1A8JtuwQsMtHAapzD5+XKWxMn01UnVPpfxH Q74g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A3TJV5nC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h13si278429ybq.411.2020.06.02.18.21.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 Jun 2020 18:21:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A3TJV5nC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgI61-0002ca-4z for patch@linaro.org; Tue, 02 Jun 2020 21:21:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgHyT-0003yC-9e for qemu-devel@nongnu.org; Tue, 02 Jun 2020 21:13:45 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:45833) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jgHyL-0003Yx-Pt for qemu-devel@nongnu.org; Tue, 02 Jun 2020 21:13:43 -0400 Received: by mail-pl1-x642.google.com with SMTP id y11so187072plt.12 for ; Tue, 02 Jun 2020 18:13:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0EIkcVZM7CTGPx7yRFPLzi2q/BnEPgFyUzrQe3RUVmw=; b=A3TJV5nCnr3oYovFU1ADFd+5yfFGhL0YsAB6KWudClLp1wvvmNicYYxE+o0VmSob5o p138YpdPOZiQNyBhJmc2bHHEra6CcwLLkoatJTvmxsPrgGSSvEAF+e1+6S886KwhNE9q DOSTP2M15CU1MV1HQMlQ4H9byezhmyDDVF6j6FHTcFkBsx+AIvklRPWXzbStPUSYl116 vacfPn1/3C3TUSMtjVRqiATU/ah4CEfQA/3gnBiXw7lLJwoW8+9ldG9hbcDDQGl27Vmu SBfWVCdk6F4oUAXCg0bSLVlM2TKvyudy1T/vvlfpgnwX87pb8GtZY9kwnZp4SzUsQ2iq 6xLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0EIkcVZM7CTGPx7yRFPLzi2q/BnEPgFyUzrQe3RUVmw=; b=Pww4HSDBFug91K8TdPhrTiA8WkwGWrZqxZRAxq4xulafm1SPNsScZnqVX32TKMzb9p qzf+JZe0rmSD2f+L47kS7mr4t+Xpwlf9KSoGdod56VWJBKgRrc3NZy66kzFGBrn/Fpsm IDejndqRGN8wVirl/HQZRYmgKb2HErW627bDm92DoM+WjVgxiYym0IuKEuXzdo9n3aC3 XX1zZ2s5rrwQbXmLvgQmeUsSs4gSJENJKDmPvFx+TTEYNAf4pDRAQjkqCfzip30hp9+G IIEpSqIqfTdiGdoit7vosVq0Rok5WV1cD/tgzOlPMTN2drNIbkcP0ZdTlN2HQjysi06f ZGmA== X-Gm-Message-State: AOAM533JIAcsULGHFEZav9g2uBwwHkhZza19h73AUiWg0SlF4zABtUTf 8rqMuZ6wRwX37lnUWfDP52Lzi+1QDYU= X-Received: by 2002:a17:902:8218:: with SMTP id x24mr27620797pln.150.1591146815640; Tue, 02 Jun 2020 18:13:35 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id 3sm290067pfe.85.2020.06.02.18.13.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 18:13:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only Date: Tue, 2 Jun 2020 18:12:48 -0700 Message-Id: <20200603011317.473934-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200603011317.473934-1-richard.henderson@linaro.org> References: <20200603011317.473934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We need this to raise unaligned exceptions from user mode. Signed-off-by: Richard Henderson --- v6: Use EXCP_UNALIGNED for user-only and update cpu_loop.c. --- linux-user/aarch64/cpu_loop.c | 7 ++++++ linux-user/arm/cpu_loop.c | 7 ++++++ target/arm/cpu.c | 2 +- target/arm/tlb_helper.c | 41 ++++++++++++++++++++++------------- 4 files changed, 41 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..3cca637bb9 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -121,6 +121,13 @@ void cpu_loop(CPUARMState *env) info._sifields._sigfault._addr = env->exception.vaddress; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_UNALIGNED: + info.si_signo = TARGET_SIGBUS; + info.si_errno = 0; + info.si_code = TARGET_BUS_ADRALN; + info._sifields._sigfault._addr = env->exception.vaddress; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; case EXCP_DEBUG: case EXCP_BKPT: info.si_signo = TARGET_SIGTRAP; diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 13629ee1f6..0d568d2d69 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -411,6 +411,13 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } break; + case EXCP_UNALIGNED: + info.si_signo = TARGET_SIGBUS; + info.si_errno = 0; + info.si_code = TARGET_BUS_ADRALN; + info._sifields._sigfault._addr = env->exception.vaddress; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; case EXCP_DEBUG: case EXCP_BKPT: excp_debug: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 32bec156f2..0f1a46f531 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2166,8 +2166,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->tlb_fill = arm_cpu_tlb_fill; cc->debug_excp_handler = arm_debug_excp_handler; cc->debug_check_watchpoint = arm_debug_check_watchpoint; -#if !defined(CONFIG_USER_ONLY) cc->do_unaligned_access = arm_cpu_do_unaligned_access; +#if !defined(CONFIG_USER_ONLY) cc->do_transaction_failed = arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7388494a55..d4e6d37f4f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -107,21 +107,6 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, raise_exception(env, exc, syn, target_el); } -/* Raise a data fault alignment exception for the specified virtual address */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - ARMCPU *cpu = ARM_CPU(cs); - ARMMMUFaultInfo fi = {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.type = ARMFault_Alignment; - arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); -} - /* * arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort @@ -198,3 +183,29 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } #endif } + +/* Raise a data fault alignment exception for the specified virtual address */ +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cpu->env.exception.vaddress = vaddr; + /* + * For HW, this is EXCP_DATA_ABORT with a proper syndrome. + * Make it easier for ourselves in linux-user/arm/cpu_loop.c. + */ + cs->exception_index = EXCP_UNALIGNED; + cpu_loop_exit_restore(cs, retaddr); +#else + ARMMMUFaultInfo fi = {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.type = ARMFault_Alignment; + arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); +#endif +}